Victim structures for predicting the ESD reliability of IO circuits

Compact, wafer-level ESD victim circuits that fail similarly to real IO circuits are used to validate the performance of ESD protection schemes in a 65-nm process technology. Electrical failure analysis identifies the device that fails during the ESD testing. Effects of circuit topologies and victim design choices on measured failure level are evaluated, and a follow-up chip is designed to extend the testing capability to CDM. The measured response of victim circuits is utilized to validate ESD compact models. Compact models are used to investigate the prediction of device failure in simulation.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois Urbana-Champaign

Year dc:date

2025

Author dc:creator

• Sear, Patrick

Contributors dc:contributor

• Rosenbaum, Elyse

• ESD
• Circuit Design

Statement dc:rights

• Copyright 2025 Patrick Sear

Language dc:language

en

Handle dc:identifier

https://hdl.handle.net/2142/132461

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/132461