Design and analysis of a 1.28ghz charge pump phase-locked loop in 180nm technology node

This thesis presents readers, especially undergraduate electrical engineering students in their junior or senior years who have solid background knowledge in Integrated Circuits (IC) design and strong passion in the semiconductor industry, with some flavors of the fundamentals of the mixed-signal IC design of a phase-locked loop (PLL) implemented in 180nm technology node and operated at a center frequency of 1.28GHz. It begins by introducing the applications and motivations of PLLs. The thesis then moves on by diving deep into the discussion of each of the PLL component’s intuition, schematic, characteristic, and linear model. Afterwards, a complete analysis of PLL is conducted, including its block diagram, linear model, stability, and characteristics, etc. The thesis finishes with the conclusion and discussion of future work to improve the PLL design.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2024

Author dc:creator

• Wang, Qiuyu

Contributors dc:contributor

• Schutt-Ainé, José E

• Phase-locked Loop
• Pll
• Mixed-signal Ic Design
• High-speed Link

Statement dc:rights

• © 2024 Qiuyu Wang

Language dc:language

en, eng

Handle dc:identifier

https://hdl.handle.net/2142/124373

OAI record oai:identifier

https://www.ideals.illinois.edu/oai-pmh?verb=GetRecord&metadataPrefix=etdms&identifier=oai%3Awww.ideals.illinois.edu%3A2142%2F124373