Machine learning approach for cascade-able nonlinear transceiver modeling and high speed link simulation

With the rapid developments in integrated circuit technology, the data rates of chip-to-chip communication are fast approaching several tens of Gb/s. While the desire for massive data-exchange is satisfied as a result of transceiver links operating at high frequency, signal integrity (SI) issues emerge due to short switching times. To identify and resolve these problems early in the production cycle, SI simulations such as time-domain transient analysis are incorporated in pre- and post-layout design stages. For efficiency concern, it is often desired to use accurate and efficient black-box macromodels of components on board instead of their SPICE-like representations. The motivation rests in the nonlinear nature of the transceivers, which oftentimes requires multiple Newton-Raphson iterations before convergence can be achieved. This thesis is meant to contribute a small part to the enormous amount of effort of the behavior modeling community in the quest for computationally efficient methods capable of handling high speed link (HSL) simulation of nonlinear devices and systems using machine learning methods. Specifically, this work reports a feed forward-neural network (FNN) approach with finite memory neurons to model nonlinear transistor level buffers. After proper training, the FNN models can be cascaded with various channels characterized by either their geometrical or scattering parameters. At each cascading node, a FNN model is applied to predict the corresponding voltage waveform and forward that prediction along the link as input for the next available model. Compared to the industrial standard models like SPICE and IBIS, HSL simulation done through FNN models does not involve complicated converging iterations, nor does it requires substantial domain knowledge. Furthermore, we demonstrated that by overlaying the high-correlation output responses from the FNN models, eye diagram analysis can now be performed in a much faster manner as opposed to the conventional SPICE circuit solvers.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2022

Author dc:creator

• Zhao, Yixuan

Contributors dc:contributor

• Schutt-Aine, Jose E
• Kudeki, Erhan
• Bernhard, Jennifer T
• Dragic, Peter D

• Transceiver Modeling
• Feed-forward Neural Network
• Cascade
• Signal Integrity
• Time-domain
• Channel Simulation.

Statement dc:rights

• Copyright 2022 Yixuan Zhao

Language dc:language

en, eng

Handle dc:identifier

https://hdl.handle.net/2142/117653

OAI record oai:identifier

https://www.ideals.illinois.edu/oai-pmh?verb=GetRecord&metadataPrefix=etdms&identifier=oai%3Awww.ideals.illinois.edu%3A2142%2F117653