Building high-performance and versatile data plane for modern data center network

In the past decade, with much higher performance (e.g., from 1Gbps to even 200Gbps), the network has become increasingly crucial in the modern data center. On the one hand, the slow-down of Moore's Law generates an increasingly large gap between the network processing capability on the conventional hardware system and the modern network performance. On the other hand, emerging network devices tend to be rich with accelerators and programmable logics, offloading software stacks and applications. This proposal tries to answer two questions from multiple perspectives: (1) how we should enhance the existing system components (e.g., CPU, network stack) to handle the fast network efficiently and (2) how we can leverage the network itself to accelerate a broader range of applications. For question one, we first propose a generic and efficient on-CPU accelerator, called QEI, for fine-grained but costly data query, a class of operation ubiquitous and diverse in data center applications. QEI leverages the common execution pattern of multiple types of queries to map them to the same hardware architecture. Also, QEI can be reconfigured to support new and customized data queries. Last, QEI's design decouples the stateful control logic from the stateless data logic and places them into the CPU in a distributed manner. All these features justify QEI's versatility and practicality for future implementation on real commodity hardware. Second, we consider how to tune the existing hardware resources for optimal performance. Specifically, we focus on the last-level cache (LLC) management. In addition to the CPU core, I/O devices, especially the network card, are also critical factors that interact with the LLC. We propose an I/O-aware LLC management mechanism, called IAT, that dynamically adjusts the LLC portion that I/O devices can leverage and selects CPU core(s) that share LLC with I/O devices. For question two, we use the reconfigurable match-action table (RMT) based programmable switch as an example to explore the processing capability. We find that due to the architectural limitations, the current commodity programmable switch is not able to process floating-point data, which is common in many distributed applications. Hence, we propose FPISA, a novel mechanism that represents and processes floating-point data on the RMT programmable switch. FPISA also includes a set of cheap but useful hardware enhancements that enables more efficient and high-precision floating-point operations.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2022

Author dc:creator

• Yuan, Yifan

Contributors dc:contributor

• Kim, Nam Sung
• Chen, Deming
• Mittal, Radhika
• Wang, Ren

• data center network
• I/O subsystem
• cache/memory hierarchy
• accelerator
• programmable network

Statement dc:rights

• Copyright 2022 Yifan Yuan

Language dc:language

en, eng

Handle dc:identifier

https://hdl.handle.net/2142/116153

OAI record oai:identifier

https://www.ideals.illinois.edu/oai-pmh?verb=GetRecord&metadataPrefix=etdms&identifier=oai%3Awww.ideals.illinois.edu%3A2142%2F116153