Hardware implementation and evaluation of the Spandex cache coherence protocol

Emerging heterogeneous hardware systems and applications that have shared data between multiple CPU cores and computation accelerators bring the need for efficient and flexible cache coherence support. Since different devices like CPUs, GPUs and accelerators have diverse memory demands and different data-sharing patterns, Spandex was proposed to efficiently integrate devices with different cache coherence protocols. The flexibility, simplicity and scalability of Spandex make it suitable for maintaining cache coherence in complicated SoCs. In addition, the introduction of Flexible Coherence Specialization (FCS) in Spandex further improves the granularity of flexibility from device granularity to address and request granularity. However, even though benchmark evaluations of Spandex in simulation have shown significant benefits, it has not been proven that Spandex will perform as well in real hardware, due to the lack of real-world RTL implementation of the protocol itself. In this work, we implement the Spandex cache coherence protocol in real hardware and evaluate its performance on real system-on-chip architectures running on FPGAs. By implementing and integrating Spandex on a real-world FPGA SoC, we advance the Spandex protocol from software simulation to a real hardware implementation. We prove its efficiency and flexibility, which are the key benefits of Spandex already proven in simulation, but on the next level down to the hardware. On the Xilinx VCU118 FPGA evaluation platform, we evaluated Spandex by running hardware-accelerated micro-benchmarks on heterogeneous SoCs with the Spandex protocol compared to the MESI protocol. On these micro-benchmarks, we see a performance improvement of up to 1.77X, and also up to 3.55X and 5.30X network traffic improvement in terms of flit count and flip-hop count respectively. We also propose the Spandex RISC-V instruction set extension, as a new interface for Spandex-aware and FCS-aware applications to convey flexible coherence performance information down to the hardware. We also provide a configuration register based interface for easily managing coherence specializations for fixed-function accelerators that are not capable of executing dynamic code. The RTL implementation, along with the accompanying RISC-V ISA support, greatly reduces the obstacles to the adoption of Spandex in the research community, and allows more system designers to consider Spandex as their coherence solution to further boost performance.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2021

Author dc:creator

• Zhu, Zeran

Contributors dc:contributor

• Adve, Sarita

• Cache Coherence Protocol
• Hardware Architecture
• Heterogeneous System-on-Chip
• High-Level Synthesis

Statement dc:rights

• Copyright 2021 Zeran Zhu

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/110588

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/110588