Inductive noise characterization and mitigation techniques for modern computer systems

As the processor market continues to diversify, and device form factor continues to change, the challenges of processor power delivery and voltage noise become increasingly difficult to address. This thesis characterizes voltage emergencies and evaluates voltage noise mitigation techniques across a range of processors and power distribution networks. Each processor class has unique design constraints that affect voltage noise to differing degrees. This work considers three processor and PDN combinations representative of the current processor market. We evaluate the voltage noise observed, and for each system we evaluate three predictive architectural techniques to mitigate voltage noise. We describe the challenges inherent to each of these techniques, and the potential improvements to the architectural techniques. We also present Predict-T, a modern simulation framework for evaluating power supply and processor interaction. The framework is useful for evaluating collaborative circuit level and architecture level noise mitigation techniques. Finally, an instruction dependency-based prediction mechanism is proposed and evaluated across the different processors.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2021

Author dc:creator

• Smith, Andrew Timothy

Contributors dc:contributor

• Kumar, Rakesh

• Inductive Noise
• Processor
• Mitigation
• Power Distribution Network
• PDN
• Voltage Noise
• Simulation

Statement dc:rights

• c 2020 Andrew Timothy Smith

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/109316

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/109316