{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/109316"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/109316","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Inductive noise characterization and mitigation techniques for modern computer systems","abstract":"As the processor market continues to diversify, and device form factor continues to change, the challenges of processor power delivery and voltage noise become increasingly difficult to address. This thesis characterizes voltage emergencies and evaluates voltage noise mitigation techniques across a range of processors and power distribution networks. Each processor class has unique design constraints that affect voltage noise to differing degrees. This work considers three processor and PDN combinations representative of the current processor market. We evaluate the voltage noise observed, and for each system we evaluate three predictive architectural techniques to mitigate voltage noise. We describe the challenges inherent to each of these techniques, and the potential improvements to the architectural techniques. We also present Predict-T, a modern simulation framework for evaluating power supply and processor interaction. The framework is useful for evaluating collaborative circuit level and architecture level noise mitigation techniques. Finally, an instruction dependency-based prediction mechanism is proposed and evaluated across the different processors.","abstract_html":"As the processor market continues to diversify, and device form factor continues to change, the challenges of processor power delivery and voltage noise become increasingly difficult to address. This thesis characterizes voltage emergencies and evaluates voltage noise mitigation techniques across a range of processors and power distribution networks. Each processor class has unique design constraints that affect voltage noise to differing degrees. This work considers three processor and PDN combinations representative of the current processor market. We evaluate the voltage noise observed, and for each system we evaluate three predictive architectural techniques to mitigate voltage noise. We describe the challenges inherent to each of these techniques, and the potential improvements to the architectural techniques. We also present Predict-T, a modern simulation framework for evaluating power supply and processor interaction. The framework is useful for evaluating collaborative circuit level and architecture level noise mitigation techniques. Finally, an instruction dependency-based prediction mechanism is proposed and evaluated across the different processors.","abstract_has_math":false,"creators":["Smith, Andrew Timothy"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Kumar, Rakesh"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2021,"date_issued":"2021-03-05T21:33:13Z","date_published":"2021-03-05T21:33:13Z","updated_at":"2026-07-22T22:24:50Z","subjects":["Inductive Noise","Processor","Mitigation","Power Distribution Network","PDN","Voltage Noise","Simulation"],"languages":["en"],"rights":["c 2020 Andrew Timothy Smith"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/109316","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Kumar, Rakesh"]},{"key":"dc:creator","label":"Author","values":["Smith, Andrew Timothy"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2021-03-05T21:33:13Z","2020-07-29","2020-12"]},{"key":"dc:type","label":"Dc Type","values":["text","Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Inductive Noise","Processor","Mitigation","Power Distribution Network","PDN","Voltage Noise","Simulation"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["c 2020 Andrew Timothy Smith"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/109316"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["As the processor market continues to diversify, and device form factor continues to change, the challenges of processor power delivery and voltage noise become increasingly difficult to address. This thesis characterizes voltage emergencies and evaluates voltage noise mitigation techniques across a range of processors and power distribution networks. Each processor class has unique design constraints that affect voltage noise to differing degrees. This work considers three processor and PDN combinations representative of the current processor market. We evaluate the voltage noise observed, and for each system we evaluate three predictive architectural techniques to mitigate voltage noise. We describe the challenges inherent to each of these techniques, and the potential improvements to the architectural techniques. We also present Predict-T, a modern simulation framework for evaluating power supply and processor interaction. The framework is useful for evaluating collaborative circuit level and architecture level noise mitigation techniques. Finally, an instruction dependency-based prediction mechanism is proposed and evaluated across the different processors.","Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2021-03-04 without embargo terms","The student, Andrew Smith, accepted the attached license on 2020-07-28 at 10:32.","The student, Andrew Smith, submitted this Thesis for approval on 2020-07-28 at 10:46.","This Thesis was approved for publication on 2020-07-29 at 16:47.","DSpace SAF Submission Ingestion Package generated from Vireo submission #15759 on 2021-03-04 at 15:32:59","Made available in DSpace on 2021-03-05T21:33:13Z (GMT). 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This thesis characterizes voltage emergencies and evaluates voltage noise mitigation techniques across a range of processors and power distribution networks. Each processor class has unique design constraints that affect voltage noise to differing degrees. This work considers three processor and PDN combinations representative of the current processor market. We evaluate the voltage noise observed, and for each system we evaluate three predictive architectural techniques to mitigate voltage noise. We describe the challenges inherent to each of these techniques, and the potential improvements to the architectural techniques. We also present Predict-T, a modern simulation framework for evaluating power supply and processor interaction. The framework is useful for evaluating collaborative circuit level and architecture level noise mitigation techniques. Finally, an instruction dependency-based prediction mechanism is proposed and evaluated across the different processors.","Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2021-03-04 without embargo terms","The student, Andrew Smith, accepted the attached license on 2020-07-28 at 10:32.","The student, Andrew Smith, submitted this Thesis for approval on 2020-07-28 at 10:46.","This Thesis was approved for publication on 2020-07-29 at 16:47.","DSpace SAF Submission Ingestion Package generated from Vireo submission #15759 on 2021-03-04 at 15:32:59","Made available in DSpace on 2021-03-05T21:33:13Z (GMT). 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