Network-on-chip design for a chiplet-based waferscale processor

Motivated by the failing of Moore’s law and Dennard scaling, as well as increasingly large parallel tasks like machine learning and big data analysis, processors continue to increase in area and incorporate more computational cores. This growth requires innovation in manufacturing processes to build larger systems, and architectural changes to enable performance to scale acceptably. One significant architectural change is the shift from bus and crossbar based processor interconnections to networks-on-chip (NoCs). This thesis details the design of an NoC to enable a shared memory architecture in a chiplet-based wafer scale processor with architectural support for up to 14,336 cores.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2020

Author dc:creator

• Cebry, Nicholas

Contributors dc:contributor

• Kumar, Rakesh

• network-on-chip
• waferscale

Statement dc:rights

• Copyright 2020 Nicholas Cebry

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/108436

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/108436