Receiver equalization for a 10 gigabit per second high-speed serial link in 65 nm CMOS technology

This thesis addresses the receiver equalization techniques for a 10 Gbps USB 3.1 link in 65 nm CMOS technology. Two types of equalizers are implemented: a continuous time linear equalizer (CTLE) and a 1-tap full-rate decision feedback equalizer (DFE). The combined CTLE and DFE architecture is simulated with an rms receiver clock jitter of 5.3 ps and achieves a BER < 10E−12 while consuming 3.3 mW at the Nyquist frequency of 5 GHz.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2019

Author dc:creator

• Rajwardan, Ashwarya

Contributors dc:contributor

• Schutt-Ainé, José E.

• DFE, CTLE, Equalizer, Signal Integrity, High-speed serial link

Statement dc:rights

• Copyright 2019 Ashwarya Rajwardan

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/104803

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/104803