{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/104803"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/104803","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Receiver equalization for a 10 gigabit per second high-speed serial link in 65 nm CMOS technology","abstract":"This thesis addresses the receiver equalization techniques for a 10 Gbps USB 3.1 link in 65 nm CMOS technology. Two types of equalizers are implemented: a continuous time linear equalizer (CTLE) and a 1-tap full-rate decision feedback equalizer (DFE). The combined CTLE and DFE architecture is simulated with an rms receiver clock jitter of 5.3 ps and achieves a BER < 10E−12 while consuming 3.3 mW at the Nyquist frequency of 5 GHz.","abstract_html":"This thesis addresses the receiver equalization techniques for a 10 Gbps USB 3.1 link in 65 nm CMOS technology. Two types of equalizers are implemented: a continuous time linear equalizer (CTLE) and a 1-tap full-rate decision feedback equalizer (DFE). The combined CTLE and DFE architecture is simulated with an rms receiver clock jitter of 5.3 ps and achieves a BER &lt; 10E−12 while consuming 3.3 mW at the Nyquist frequency of 5 GHz.","abstract_has_math":false,"creators":["Rajwardan, Ashwarya"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Schutt-Ainé, José E."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2019,"date_issued":"2019-08-23T19:51:46Z","date_published":"2019-08-23T19:51:46Z","updated_at":"2026-07-22T22:24:42Z","subjects":["DFE, CTLE, Equalizer, Signal Integrity, High-speed serial link"],"languages":["en"],"rights":["Copyright 2019 Ashwarya Rajwardan"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/104803","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Schutt-Ainé, José E."]},{"key":"dc:creator","label":"Author","values":["Rajwardan, Ashwarya"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2019-08-23T19:51:46Z","2019-04-11","2019-05"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["DFE, CTLE, Equalizer, Signal Integrity, High-speed serial link"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2019 Ashwarya Rajwardan"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/104803"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["This thesis addresses the receiver equalization techniques for a 10 Gbps USB 3.1 link in 65 nm CMOS technology. Two types of equalizers are implemented: a continuous time linear equalizer (CTLE) and a 1-tap full-rate decision feedback equalizer (DFE). The combined CTLE and DFE architecture is simulated with an rms receiver clock jitter of 5.3 ps and achieves a BER < 10E−12 while consuming 3.3 mW at the Nyquist frequency of 5 GHz.","Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2019-08-22 without embargo terms","The student, Ashwarya Rajwardan, accepted the attached license on 2019-04-10 at 16:22.","The student, Ashwarya Rajwardan, submitted this Thesis for approval on 2019-04-10 at 16:23.","This Thesis was approved for publication on 2019-04-11 at 18:01.","DSpace SAF Submission Ingestion Package generated from Vireo submission #13554 on 2019-08-22 at 14:42:29","Made available in DSpace on 2019-08-23T19:51:46Z (GMT). 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