Enhanced modeling methodology for system-level electrostatic discharge simulation

To enable accurate system-level electrostatic discharge (ESD) simulation, models for the equipment under test, the ESD source, and the environment are required. This work presents advanced modeling methods for the ESD source, the victim IC, and other on-board components, most notably the transient voltage suppressor. Kernel regression is used to generate an enhanced quasistatic I-V model of an IC pin, which reflects its dependency on the circuit board’s power delivery network. S-parameter measurements enable the development of a model for an IEC 61000-4-2 ESD source that comprehends the coupling among the ground straps and the ground plane. The transient-voltage-suppressor device is modeled using a behavioral snapback model that shows better convergence in circuit simulation than piece-wise models. Furthermore, ESD-induced soft failures are often caused by the noise coupled between the IC package traces. To help identify this type of failure, a hybrid electromagnetic and circuit simulation approach is demonstrated.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2019

Author dc:creator

• Xiong, Jie

Contributors dc:contributor

• Rosenbaum, Elyse

• Electrostatic discharge
• System-efficient ESD design
• IEC 61000-4-2 discharge
• TLP characterization

Statement dc:rights

• Copyright 2019 Jie Xiong

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/104725

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/104725