MNA stamping for transient circuit simulation using SPICE

Simulation is an essential step in the circuit design procedure, helping to verify the behavior of a designed circuit and dramatically reducing the time and effort required for debugging a given design. However, to analyze this behavior, we require an interface between the circuit design and the computer’s computational capabilities. This translation can be done in various ways depending on what aspect of the circuit is desired to be modeled (steady-state, transient, etc.). In this thesis, we explore two of these (steady-state MNA formulation and State-Space formulation) as a first step towards transient analysis.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2019

Author dc:creator

• Verma, Vishesh

Contributors dc:contributor

• Schutt-Ainé, José E.

• MNA
• Stamping
• SPICE
• simulation

Statement dc:rights

• Copyright 2018 Vishesh Verma

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/102467

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/102467