Minimization Of Power Dissipation In Digital Circuits Using Pipelining And A Study Of Clock Gating Technique

Power dissipation is one of the major design issues of digital circuits. The power dissipated by a circuit affects its speed and performance. Multiplier is one of the most commonly used circuits in the digital devices. There are various types of multipliers available depending upon the application in which they are used. In the present thesis report, the importance of power dissipation in today's digital technology is discussed and the various types and sources of power dissipation have been elaborated. Different types of multipliers have been designed which vary in their structure and amount of power dissipation. The concept of pipelining is explained and the reduction in the power dissipation of the multipliers after pipelining is experimentally determined. Clock gating is a very important technique used in the design of digital circuits to reduce power dissipation. Various types of clock gating techniques have been presented as a case study. The technology used in the simulation of these circuits is 0.35µm CMOS and the simulator used is SPECTRE S.

Author dc:creator

• Panchangam, Ranganath

Contributors dc:contributor

• Yuan, Jiann S.

• Dissertations
• Academic -- Engineering and Computer Science
• Engineering and Computer Science -- Dissertations
• Academic
• Clock gating
• Digital circuits
• Pipelining
• Power dissipation
• Electrical and Computer Engineering
• Engineering
• Dissertations, Academic -- Engineering and Computer Science; Engineering and Computer Science -- Dissertations, Academic

Language dc:language

English

Identifier

CFE0000130

OAI identifier oai:identifier

oai:stars.library.ucf.edu:etd-1146