Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 18 of 18 for “"Clock-gating"”.
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VAST-LP: clock gating in high-level synthesis
… HLS engine VAST and propose a method to generate clock-gating-friendly RTL code for downstream logic synthesis tools. We use one-hot-key encoding method to build the state tran- sition in hardware, and we use the state registers along with main clock signal to generate subclock signals. By …
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Minimization Of Power Dissipation In Digital Circuits Using Pipelining And A Study Of Clock Gating Technique
… after pipelining is experimentally determined. Clock gating is a very important technique used in the design of digital circuits to reduce power dissipation. Various types of clock gating techniques have been presented as a case study. The technology used in the simulation of these circuits is …
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High Level Power Estimation and Reduction Techniques for Power Aware Hardware Design
… savings opportunities are traditional such as clock-gating, operand-isolation etc. The exploration of alternate granularities of these techniques with target applications in mind, opens the door for traditional power reduction opportunities at the high-level. This work therefore concentrates on …
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Clock gatting for latch based design
… de reducción de potencia mas exitosas es clock-gating cuyo objetivo es reducir el consumo de potencia generado por las transiciones debidas a la señal de clk. La reducción de potencia se logra mediante la inserción de clock-gating cells (celdas de clock-gating) que impiden que la señal de …
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On a Viterbi decoder design for low power dissipation
… design environment. We considered two methods, clock-gating and toggle-filtering, in our design. A Viterbi decoder consists of five blocks. The clock-gating was applied to the survivor path storage block and the toggle-filtering to the trace-back block of a Viterbi decoder. We followed the …
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Adiabatic Circuits for Power-Constrained Cryptographic Computations
… due to high energy dissipation of the Power-Clock Generator (PCG) and complexity of the multi-phase power-clocking scheme. Energy efficiency of the adiabatic system is often degraded due to the high energy dissipation of the PCG. In this thesis, nstep charging strategy using tank capacitors …
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Low-power digital processor for wireless sensor networks
… hardwired algorithms, lowered supply voltages, clock gating and subsystem shutdown. Prototypes were built on both a FPGA and ASIC platform, in order to verify functionality and characterize power consumption. The resulting 0.18[micro]m silicon fabricated in National Semiconductor Corporation's …
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Strategies for Performance and Quality Improvement of Hardware Verification and Synthesis Algorithms
… approaches for Observability Dont Care (ODC) clock gating. Moreover we intelligently choose those inductive invariants candidates such that their validation will benefit the purpose in clock-gating-based low-power design.
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Formal Approaches to Globally Asynchronous and Locally Synchronous Design
… which makes implementing a synchronous global clock difficult, and power consuming. As a result, globally asynchronous and locally synchronous (GALS) designs have been proposed for future SoCs. Second, due to time-to-market pressure, and productivity gain, intellectual property (IP) block reuse …
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Hardware implementation of a low-power two-dimensional discrete cosine transform
… with distributed arithmetic. It features clock gating schemes as well as power-aware schemes that utilize input correlations to dynamically scale down power consumption. This is done by eliminating glitching in the ROM Accumulate (RAC) units to effectively stop unnecessary computation. The …
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On the Low Power Design of DCT and IDCT for Low Bit Rate Video Codecs
… IDCT input, low precision constant multipliers, clock gating, and a low transition data path. Gate-level simulations characterize the effectiveness of each technique. The combination of all techniques reduces average power dissipation by 95% over the baseline reference DCT and IDCT blocks.
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Task scheduling in high-level synthesis
… localized shutdown of functional modules by clock gating to reduce power consumption. Since CMOS circuits consume only a negligible amount of power when they are not switching, inhibiting unnecessary circuit switching activities in functional modules and clock signals will lead to a reduction …
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Low power data-dependent transform video and still image coding
… IDCT computation algorithm along with clock gating techniques are used to reduce the number of arithmetic operations for video inputs. The second chip is a DCT core processor that exhibits two innovative techniques for arithmetic operation reduction in the DCT computation context along …
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Algorithm-circuit co-design for detecting symptomatic patterns in biological signals
… techniques at circuit level such as power and clock gating are utilized along with error resiliency at algorithm level to implement these algorithms in TSMC $65$nm bulk-Si technology. Furthermore, the methodology is extended to develop a generic pattern detection system, which could be used for …
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Design Automation Flow for Voltage Adaptive Light Vth Hopping for Leakage Minimization in Sequential Circuits
… Leakage Control (RALC) techniques like Power Gating (PG) and Reverse Body Biasing (RBB) being the primary candidates for RALC, PG is found to give better leakage savings than RBB and hence is a popular technique in the industry.</p><p> Comparing PG and RBB techniques, RBB has less overhead and …
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Self-tuning dynamic voltage scaling techniques for processor design
… by using conventional speed-binning process with clock duty-cycle modulation. Second, we propose a new direct CPM that is based on a non-speculative pre-sampling technique. A processor that is based on this technique predicts timing errors in the actual critical paths and undertakes preventive …
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Analysis and Mitigation of Multiple Radiation Induced Errors in Modern Circuits
… may lose the data stored in the element during clock gating due to high impedance states or are vulnerable to an error after a DNU occurs. In this dissertation, a novel latch design is proposed in which all nodes are capable of fully recovering their correct value after a single or double node …
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Acquisition systems and decoding algorithms of peripheral neural signals for prosthetic applications
… only by using complex hardware platforms clocked at very high operating frequencies which are not be compliant with the low-power requirements needed to allow portability for the prosthetic device. At present, in fact, the important aspect of the real-time implementation of sophisticated …