ENERGY EFFICIENT CIRCUIT TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER ADC

Charge-scaling (CS) successive approximation register (SAR) ADC's are widely used in the design of low power electronics. Significant portions of CS-SAR ADC power are consumed by CS capacitor arrays and comparator circuits. This Dissertation presents circuit techniques to reduce the power consumption of both CS capacitor array and the latch comparator during ADC operations. The impacts of the proposed techniques on ADC accuracies are analyzed and circuit techniques are presented to address the accuracy concerns. The dissertation also presents techniques to cope with capacitor mismatches, which becomes more significant with the use of very small unit capacitors in the CS array. These techniques rely on a novel programmable CS capacitor array that allow optimally grouping the unit capacitors. Based on a 0.13um CMOS technology the proposed techniques are verified with extensive circuit simulation. Post layout simulations are done to evaluate the proposed techniques for energy efficient CS capacitor array.

Name thesis:degree_name

Doctor of Philosophy

Level thesis:degree_level

Campus Only Dissertation

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Year

2012

Author dc:creator

• Kandala, Veera Raghavendra Sai Mallik

Contributors dc:contributor

• Wang, Haibo

• CIRCUIT TECHNIQUES
• HIGH SPEED
• LOW POWER
• LOW VOLTAGE
• RAIL-TO-RAIL COMPARATOR
• SAR ADC

Repository record dc:identifier

https://opensiuc.lib.siu.edu/dissertations/539

OAI identifier oai:identifier

oai:opensiuc.lib.siu.edu:dissertations-1540