{"id":{"repo_id":"siu-theses","oai_identifier":"oai:opensiuc.lib.siu.edu:dissertations-1540"},"canonical_url":"https://search.dev.ndltd.org/etd/siu-theses/oai:opensiuc.lib.siu.edu:dissertations-1540","repository":{"repo_id":"siu-theses","name":"Southern Illinois University","base_url":"https://opensiuc.lib.siu.edu/do/oai/"},"display":{"title":"ENERGY EFFICIENT CIRCUIT TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER ADC","abstract":"Charge-scaling (CS) successive approximation register (SAR) ADC's are widely used in the design of low power electronics. Significant portions of CS-SAR ADC power are consumed by CS capacitor arrays and comparator circuits. This Dissertation presents circuit techniques to reduce the power consumption of both CS capacitor array and the latch comparator during ADC operations. The impacts of the proposed techniques on ADC accuracies are analyzed and circuit techniques are presented to address the accuracy concerns. The dissertation also presents techniques to cope with capacitor mismatches, which becomes more significant with the use of very small unit capacitors in the CS array. These techniques rely on a novel programmable CS capacitor array that allow optimally grouping the unit capacitors. Based on a 0.13um CMOS technology the proposed techniques are verified with extensive circuit simulation. Post layout simulations are done to evaluate the proposed techniques for energy efficient CS capacitor array.","abstract_html":"Charge-scaling (CS) successive approximation register (SAR) ADC's are widely used in the design of low power electronics. Significant portions of CS-SAR ADC power are consumed by CS capacitor arrays and comparator circuits. This Dissertation presents circuit techniques to reduce the power consumption of both CS capacitor array and the latch comparator during ADC operations. The impacts of the proposed techniques on ADC accuracies are analyzed and circuit techniques are presented to address the accuracy concerns. The dissertation also presents techniques to cope with capacitor mismatches, which becomes more significant with the use of very small unit capacitors in the CS array. These techniques rely on a novel programmable CS capacitor array that allow optimally grouping the unit capacitors. Based on a 0.13um CMOS technology the proposed techniques are verified with extensive circuit simulation. Post layout simulations are done to evaluate the proposed techniques for energy efficient CS capacitor array.","abstract_has_math":false,"creators":["Kandala, Veera Raghavendra Sai Mallik"],"institution":null,"degree_name":"Doctor of Philosophy","degree_level":"Campus Only Dissertation","degree_discipline":"Electrical and Computer Engineering","degree_department":null,"school":null,"contributors":["Wang, Haibo"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2012,"date_issued":"2012-08-01T07:00:00Z","date_published":"2012-08-01T07:00:00Z","updated_at":"2026-07-24T04:34:03Z","subjects":["CIRCUIT TECHNIQUES","HIGH SPEED","LOW POWER","LOW VOLTAGE","RAIL-TO-RAIL COMPARATOR","SAR ADC"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://opensiuc.lib.siu.edu/dissertations/539","outbound_label":"Repository record","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Wang, Haibo"]},{"key":"dc:creator","label":"Author","values":["Kandala, Veera Raghavendra Sai Mallik"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical and Computer Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Campus Only Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Doctor of Philosophy"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["CIRCUIT TECHNIQUES","HIGH SPEED","LOW POWER","LOW VOLTAGE","RAIL-TO-RAIL COMPARATOR","SAR ADC"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://opensiuc.lib.siu.edu/dissertations/539"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["Charge-scaling (CS) successive approximation register (SAR) ADC's are widely used in the design of low power electronics. Significant portions of CS-SAR ADC power are consumed by CS capacitor arrays and comparator circuits. This Dissertation presents circuit techniques to reduce the power consumption of both CS capacitor array and the latch comparator during ADC operations. The impacts of the proposed techniques on ADC accuracies are analyzed and circuit techniques are presented to address the accuracy concerns. The dissertation also presents techniques to cope with capacitor mismatches, which becomes more significant with the use of very small unit capacitors in the CS array. These techniques rely on a novel programmable CS capacitor array that allow optimally grouping the unit capacitors. Based on a 0.13um CMOS technology the proposed techniques are verified with extensive circuit simulation. Post layout simulations are done to evaluate the proposed techniques for energy efficient CS capacitor array."]},{"key":"dc:title","label":"Title","values":["ENERGY EFFICIENT CIRCUIT TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER ADC"]}]}],"canonical_facts":{"dc:contributor":["Wang, Haibo"],"dc:creator":["Kandala, Veera Raghavendra Sai Mallik"],"dc:description.abstract":["Charge-scaling (CS) successive approximation register (SAR) ADC's are widely used in the design of low power electronics. Significant portions of CS-SAR ADC power are consumed by CS capacitor arrays and comparator circuits. This Dissertation presents circuit techniques to reduce the power consumption of both CS capacitor array and the latch comparator during ADC operations. The impacts of the proposed techniques on ADC accuracies are analyzed and circuit techniques are presented to address the accuracy concerns. The dissertation also presents techniques to cope with capacitor mismatches, which becomes more significant with the use of very small unit capacitors in the CS array. These techniques rely on a novel programmable CS capacitor array that allow optimally grouping the unit capacitors. Based on a 0.13um CMOS technology the proposed techniques are verified with extensive circuit simulation. Post layout simulations are done to evaluate the proposed techniques for energy efficient CS capacitor array."],"dc:identifier":["https://opensiuc.lib.siu.edu/dissertations/539"],"dc:subject":["CIRCUIT TECHNIQUES","HIGH SPEED","LOW POWER","LOW VOLTAGE","RAIL-TO-RAIL COMPARATOR","SAR ADC"],"dc:title":["ENERGY EFFICIENT CIRCUIT TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER ADC"],"thesis:degree_discipline":["Electrical and Computer Engineering"],"thesis:degree_level":["Campus Only Dissertation"],"thesis:degree_name":["Doctor of Philosophy"]},"updated_at":"2026-07-24T04:34:03Z"}