FPGA Hardware Accelerators - Case Study on Design Methodologies and Trade-Offs

Ryan, Matthew V

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Rochester Institute of Technology

FPGA Hardware Accelerators - Case Study on Design Methodologies and Trade-Offs

dc:creator Ryan, Matthew V

thesis:degree_name Electrical Engineering (MS)

Degree

thesis:*

Name thesis:degree_name: Electrical Engineering (MS)
Level thesis:degree_level: Thesis

Author and committee

dc:creator, dc:contributor.*

Author dc:creator: Ryan, Matthew V
Contributors dc:contributor: Marcin Lukowiak

Subjects

dc:subject × 7

FPGA
HDL
Reconfigurable
Field programmable gate arrays--Design and construction
Computer input-output equipment--Design and construction
High performance computing
Electronic Devices and Semiconductor Manufacturing

Identifiers

dc:identifier.*

Repository record dc:identifier: https://repository.rit.edu/theses/959
OAI identifier oai:identifier: oai:repository.rit.edu:theses-1963

Chain of custody

source

Harvested from: Rochester Institute of Technology
Base URL: repository.rit.edu/do/oai/
Last updated: 2026-07-27
Source record: OAI-PMH GetRecord

related terms

FPGA
HDL
Reconfigurable
rit
Thesis

citation

Ryan, Matthew V. FPGA Hardware Accelerators - Case Study on Design Methodologies and Trade-Offs. Thesis thesis, https://repository.rit.edu/theses/959

FPGA Hardware Accelerators - Case Study on Design Methodologies and Trade-Offs

Degree

Author and committee

Subjects

Identifiers

Chain of custody

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