Secure Circuits: Efficient hardware countermeasures against physical side-channel attacks

The adoption of Artificial Intelligence (AI) and IoT devices has seen unprecedented growth in recent times. AI engines demand more processing capabilities while simultaneously handling sensitive user information and proprietary IP. Concurrently, IoT devices generate vast amounts of sensitive data, necessitating robust security measures to safeguard against breaches and ensure data privacy. Hence, there is a definitive need for faster and more secure systems. We present two key implementations that address the problem. Firstly, we introduce MBSNTT (Multi-Bit Serial Number Theoretic Transform Accelerator) to accelerate the NTT operation in Homomorphic Encryption. In this implementation, we apply processing-in-memory techniques to the NTT operation, thereby achieving high parallelism. In the second design, namely HDCIM (Hybrid Security-based Digital Compute in Memory Accelerator for Protected Inference), we propose hybrid security by applying mathematical masking techniques to neural network operations and closing the security gaps with low-overhead physical security measures.

Name thesis:degree_name

Master of Science

Level thesis:degree_level

Masters

Discipline thesis:degree_discipline

Engineering

Grantor

Rice University

Year dc:date.issued

2024

Author dc:creator

• Pakala, Akhil

Advisor dc:contributor.advisor

• Yang, Kaiyuan

• In-Memory Computing
• Cryptography
• Homomorphic Encryption
• NTT
• SRAM
• Masking
• Neural Networks
• Machine Learning
• Physical security

Statement dc:rights

• Copyright is held by the author, unless otherwise indicated. Permission to reuse, publish, or reproduce the work beyond the bounds of fair use or other exemptions to copyright law must be obtained from the copyright holder.

Language dc:language.iso

eng

Handle dc:identifier.uri

https://hdl.handle.net/1911/118164

OAI identifier oai:identifier

oai:repository.rice.edu:1911/118164