{"id":{"repo_id":"rice","oai_identifier":"oai:repository.rice.edu:1911/118164"},"canonical_url":"https://search.dev.ndltd.org/etd/rice/oai:repository.rice.edu:1911/118164","repository":{"repo_id":"rice","name":"Rice University","base_url":"https://repository.rice.edu/server/oai/request"},"display":{"title":"Secure Circuits: Efficient hardware countermeasures against physical side-channel attacks","abstract":"The adoption of Artificial Intelligence (AI) and IoT devices has seen unprecedented growth in recent times. AI engines demand more processing capabilities while simultaneously handling sensitive user information and proprietary IP. Concurrently, IoT devices generate vast amounts of sensitive data, necessitating robust security measures to safeguard against breaches and ensure data privacy. Hence, there is a definitive need for faster and more secure systems. We present two key implementations that address the problem. Firstly, we introduce MBSNTT (Multi-Bit Serial Number Theoretic Transform Accelerator) to accelerate the NTT operation in Homomorphic Encryption. In this implementation, we apply processing-in-memory techniques to the NTT operation, thereby achieving high parallelism. In the second design, namely HDCIM (Hybrid Security-based Digital Compute in Memory Accelerator for Protected Inference), we propose hybrid security by applying mathematical masking techniques to neural network operations and closing the security gaps with low-overhead physical security measures.","abstract_html":"The adoption of Artificial Intelligence (AI) and IoT devices has seen unprecedented growth in recent times. AI engines demand more processing capabilities while simultaneously handling sensitive user information and proprietary IP. Concurrently, IoT devices generate vast amounts of sensitive data, necessitating robust security measures to safeguard against breaches and ensure data privacy. Hence, there is a definitive need for faster and more secure systems. We present two key implementations that address the problem. Firstly, we introduce MBSNTT (Multi-Bit Serial Number Theoretic Transform Accelerator) to accelerate the NTT operation in Homomorphic Encryption. In this implementation, we apply processing-in-memory techniques to the NTT operation, thereby achieving high parallelism. In the second design, namely HDCIM (Hybrid Security-based Digital Compute in Memory Accelerator for Protected Inference), we propose hybrid security by applying mathematical masking techniques to neural network operations and closing the security gaps with low-overhead physical security measures.","abstract_has_math":false,"creators":["Pakala, Akhil"],"institution":"Rice University","degree_name":"Master of Science","degree_level":"Masters","degree_discipline":"Engineering","degree_department":null,"school":null,"contributors":[],"advisors":["Yang, Kaiyuan"],"committee_chairs":[],"committee_members":[],"year":2024,"date_issued":"2024-08-12","date_published":"2024-08-12","updated_at":"2026-07-24T04:10:24Z","subjects":["In-Memory Computing","Cryptography","Homomorphic Encryption","NTT","SRAM","Masking","Neural Networks","Machine Learning","Physical security"],"languages":["eng"],"rights":["Copyright is held by the author, unless otherwise indicated. Permission to reuse, publish, or reproduce the work beyond the bounds of fair use or other exemptions to copyright law must be obtained from the copyright holder."],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/1911/118164","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Yang, Kaiyuan"]},{"key":"dc:creator","label":"Author","values":["Pakala, Akhil"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2025-01-16T19:31:45Z"]},{"key":"dc:date.issued","label":"Date","values":["2024-08-12"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Masters"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master of Science"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["Rice University"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["In-Memory Computing","Cryptography","Homomorphic Encryption","NTT","SRAM","Masking","Neural Networks","Machine Learning","Physical security"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright is held by the author, unless otherwise indicated. Permission to reuse, publish, or reproduce the work beyond the bounds of fair use or other exemptions to copyright law must be obtained from the copyright holder."]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["https://hdl.handle.net/1911/118164"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["The adoption of Artificial Intelligence (AI) and IoT devices has seen unprecedented growth in recent times. AI engines demand more processing capabilities while simultaneously handling sensitive user information and proprietary IP. Concurrently, IoT devices generate vast amounts of sensitive data, necessitating robust security measures to safeguard against breaches and ensure data privacy. Hence, there is a definitive need for faster and more secure systems. We present two key implementations that address the problem. Firstly, we introduce MBSNTT (Multi-Bit Serial Number Theoretic Transform Accelerator) to accelerate the NTT operation in Homomorphic Encryption. In this implementation, we apply processing-in-memory techniques to the NTT operation, thereby achieving high parallelism. In the second design, namely HDCIM (Hybrid Security-based Digital Compute in Memory Accelerator for Protected Inference), we propose hybrid security by applying mathematical masking techniques to neural network operations and closing the security gaps with low-overhead physical security measures."]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Secure Circuits: Efficient hardware countermeasures against physical side-channel attacks"]}]}],"canonical_facts":{"dc:contributor.advisor":["Yang, Kaiyuan"],"dc:creator":["Pakala, Akhil"],"dc:date.accessioned":["2025-01-16T19:31:45Z"],"dc:date.issued":["2024-08-12"],"dc:description.abstract":["The adoption of Artificial Intelligence (AI) and IoT devices has seen unprecedented growth in recent times. AI engines demand more processing capabilities while simultaneously handling sensitive user information and proprietary IP. Concurrently, IoT devices generate vast amounts of sensitive data, necessitating robust security measures to safeguard against breaches and ensure data privacy. Hence, there is a definitive need for faster and more secure systems. We present two key implementations that address the problem. Firstly, we introduce MBSNTT (Multi-Bit Serial Number Theoretic Transform Accelerator) to accelerate the NTT operation in Homomorphic Encryption. In this implementation, we apply processing-in-memory techniques to the NTT operation, thereby achieving high parallelism. In the second design, namely HDCIM (Hybrid Security-based Digital Compute in Memory Accelerator for Protected Inference), we propose hybrid security by applying mathematical masking techniques to neural network operations and closing the security gaps with low-overhead physical security measures."],"dc:format.mimetype":["application/pdf"],"dc:identifier.uri":["https://hdl.handle.net/1911/118164"],"dc:language.iso":["eng"],"dc:rights":["Copyright is held by the author, unless otherwise indicated. Permission to reuse, publish, or reproduce the work beyond the bounds of fair use or other exemptions to copyright law must be obtained from the copyright holder."],"dc:subject":["In-Memory Computing","Cryptography","Homomorphic Encryption","NTT","SRAM","Masking","Neural Networks","Machine Learning","Physical security"],"dc:title":["Secure Circuits: Efficient hardware countermeasures against physical side-channel attacks"],"dc:type":["Thesis"],"thesis:degree_discipline":["Engineering"],"thesis:degree_level":["Masters"],"thesis:degree_name":["Master of Science"],"thesis:institution_name":["Rice University"]},"updated_at":"2026-07-24T04:10:24Z"}