Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 73 for “"SRAM"”.
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Scalable SRAM design
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.
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Fault tolerant, low voltage SRAM design
… problem. Static Random Access Memories (SRAMs) play a significant role in circuit power consumption and reliability of digital circuits. This thesis focuses on fault tolerant and low voltage SRAM design. A double error correcting binary BCH codec is chosen to mitigate reliability …
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Energy efficient reconfigurable SRAM using data-dependency
… bit-lines of the Static Random Access Memory (SRAM) is reduced with minimal area overhead. Additionally, multiple prediction schemes are incorporated into this framework wherein statistical data features are used to optimally configure each column of the proposed SRAM. Analysis tools for …
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Development of a Low-Power SRAM Compiler
… to the design of low-power, high-performance SRAMs (Static Random Access Memories) since they are a critical component in both hand-held devices and high-performance processors. A key in improving the performance of the system is to use an optimum sized SRAM. In this thesis, an SRAM compiler …
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Energy-efficient SRAM design in 28nm FDSOI Technology
… become more prominent. This is very critical in SRAMs, which use very small transistor dimensions to achieve high memory density. The conventional 6T SRAM bit-cell, which provides the smallest cell-area, fails to operate at lower supply voltages (Vdd). This is due to the significant degradation …
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Ultra-dynamic voltage scalable (U-DVS) SRAM design considerations
… digital systems, Static Random Access Memories (SRAMs), dominate the power consumption and area of modern integrated circuits. Consequently, designing low-power high density SRAMs operational at low voltage levels is an important research problem. This thesis focuses on and makes several …
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A hierarchical adaptively boosted in-memory classifier in 6T SRAM
Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2019-08-22 without embargo terms
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Design of resonant-tunneling diodes for a GaAs integrated SRAM
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1996.
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Ultra-low-power SRAM design in high variability advanced CMOS
Embedded SRAMs are a critical component in modern digital systems, and their role is preferentially increasing. As a result, SRAMs strongly impact the overall power, performance, and area, and, in order to manage these severely constrained trade-offs, they must be specially designed for target …
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Comprehensive variation-aware aging simulator for logic timing and SRAM stability
This research developed a framework which analyzes circuit-level reliability and evaluates the lifetimes of complex systems like state-of-art microprocessors. The novelty of the proposed work lies on its statistical timing analyzer and the ability to handle the combined effect of a variety of …
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Efficient CNNs and Energy Efficient SRAM Design for ubiquitous medical devices
… energy efficient static random access memory (SRAM) with in-memory dot-product computation for low-power segmentation network implementation. The aim is to develop platform technology embodiments deployable across a wide range of health-monitoring wearable device applications requiring …
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Stability analysis for SRAM cells with TSV induced stress in 3D ICs
… be studied for the widely used 6-transistor (6T) SRAM cell. Simulation results in this study show that static noise margin (SNM), Read Margin (RM) and write margin (WM) tend to increase with decreasing electron mobility or increasing hole mobility. Considering TSV-induced stress, we propose that …
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Silicon Germanium SRAM and ROM Designs for Wide Temperature Range Space Applications
… and feature requirements to embeddable blocks of SRAM and ROM designs from 64 bytes to 1 kilobyte that are suitable for lunar environments. The design uses the IBM SiGe 5AM BiCMOS 0.5 micron process for a synchronous memory system capable of operating at a clock frequency of 25 MHz. Radiation …
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Low-power and application-specific SRAM design for energy-efficient motion estimation
… critical than ever before for mobile devices. SRAMs are critical components in almost all SoCs affecting the overall energy-efficiency. This thesis focuses on algorithm and architecture development as well as low-power and application-specific SRAM design targeting motion estimation. First, a …
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Fault tolerant design implementation on radiation hardened by design SRAM-Based FPGAs
SRAM-based FPGAs are highly attractive for space applications due to their in-flight reconfigurability, decreased development time and cost, and increased design and testing flexibility. The Xilinx Virtex-5QV is the first commercially available Radiation Hardened By Design (RHBD) SRAM-based FPGA; …
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Study of design tradeoffs of DRAM and SRAM memories, using HSPICE computer simulation
… simulation software, HSPICE, to observe DRAM and SRAM waveforms. With TSMC 0.18 micron technology, minimum cycle times of 2.1 ins (DRAM) and 1.1 8ns (SRAM) were achieved (Cbl = 100FF), by optimizing the kr values of the SA transistors, for a fixed SA area of 1 micrometer and finding the optimum PC …
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The Art of SRAM Security: Tactics for Remanence-based Attack and Strategies for Defense
… behavior and architectural design choices impact SRAM's data remanence and its implications for security. This dissertation not only identifies new vulnerabilities due to SRAM data remanence but also paves the way for novel security solutions in the ongoing "security arms race". I present an …
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Novel Non Precharging Single Bitline 8T Static Random Access Memory
Novel 8T SRAM design, employs individual bit-line (BL) and word-line (WL) for each operation. The read operation uses read word-line (RWL) and read bit-line (RBL) respectively. On other hand the write operation employs write word-line (WWL) and write bit line (WBL). Due to single BL and WL the …
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Static random-access memory designs based on different FinFET at lower technology node (7nm)
The Static Random-Access Memory (SRAM) has a significant performance impact on current nanoelectronics systems. To improve SRAM efficiency, it is important to utilize emerging technologies to overcome short-channel effects (SCE) of conventional CMOS. FinFET devices are promising emerging devices …
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Circuit design for embedded memory in low-power integrated circuits
… embedded static random access memory (SRAM) and non-volatile memory-based on ferroelectric capacitor technology-into lowpower integrated circuits. First considered is the impact of process variation in deep-submicron technologies on SRAM, which must exhibit higher density and …
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