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National University of Singapore
GATE DIELECTRIC BREAKDOWN - 2D MODELING OF THE DBIE IMPACT ON THE DEVICE CHARACTERISTICS
Abstract
dc:description.abstractA model based on the simulation of NMOS structures has been developed to study the experimental observation on the failure mechanisms of ultrathin dielectric gate breakdown during constant voltage stress. It is verified that the dielectric breakdown induce epitaxy (DBIE) plays an important role in the device electrical behavior after breakdown. Our model is helpful in the study of the breakdown types under different stress conditions.
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
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- CAO YU