Implementation of ACCI Test Vehicle

The main challenge in commissioning a spacecraft system is the time it takes to design, build, integrate, launch, and bring online a given system. Air Force Research Lab (AFRL) has envisaged transforming these processes into what it calls “six-day spacecraft†in the next decade. The six-day spacecraft is basically getting a spacecraft part up and running in less than a week. This fast method of implementing a spacecraft system based on plug-and–play (PnP) approach, dubbed Space Plug-and-Play Avionics (SPA), will also make the space system more robust in line with an increased requirement for communication channels to have good signal integrity and high-speed data paths, like for a spacecraft radio-frequency (RF) communications with the ground command center and the gunship. AC coupled interconnects (ACCIs) provide transceivers that provide clean and boosted high-speed data by blocking noise (DC components). How good these ACCI channels work can be determined based on Bit Error Rate (BER). We have implemented ACCI Test Vehicle to be used as a high-speed data transceiver inside a spacecraft. An existing Bit Error Rate Test (BERT) system has been upgraded and redesigned to work with the implemented ACCI Test Vehicle to verify data integrity. This thesis mostly focuses on describing the implementation of ACCI Test Vehicle through integration of Appliqué Sensor Interface Module (ASIM) that bridge between Space Plug-and-Play Avionics using USB (SPA-U) and useful services for creating the SPA devices. The redesigned and upgraded FPGA-based application that runs on a PowerPC processor creates stress by sending Pseudo-Random Bit Sequences (PRBS) into several ACCI channels and assesses the performance of these channels. The designed application that had been intended to have a maximum data rate of 3.2Gbps with user-configurable and International Telecommunication Union-Telecommunication section (ITU-T) recommended PRBS test patterns didn’t work and we had to go back to a fallback option that provided relatively lower data rate. The complete system is implemented and tested on the designed ACCI Test Vehicle board running on Virtex II Pro Field Programmable Gate Array (FPGA). The logic modification for the BERT has been made in Verilog as there has been substantial hardware complexity compared to the original BERT design and, due to version upgrades the changes to the C-based drivers were made for the on-chip PowerPC processor to handle hardware routines. The BERT application allows the user to remotely configure the system and see BER test statistics through an RS232 interface. The ACCI Test Vehicle has been designed in two separate multi-layered boards; daughterboard and motherboard. The motherboard houses the ASIM as one of its components for a centralized management of the sensor or the ACCI system for resources, including power management among many other things. This paper tries to show the overall design of the ACCI Test System that provides a full plug-n-play integration with ASIM using Satellite Data Model (SDM). This implemented system demonstrates new simplified dimensions to avionics and digital development challenges.

Author dc:creator

• Lammade, Akalu Lentiro

Advisors dc:contributor.advisor

• Dr Paul Franzon, Committee Chair
• Dr Rhett Davis, Committee Member
• Dr Kevin Gard, Committee Member

• ISE
• XPS
• ACCI
• BERT
• Xilinx
• C
• ASIM
• FPGA
• Verilog

Statement dc:rights

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Dc Identifier Other

etd-05232008-091342

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