Energy-Efficient On-Chip Cache Architectures and Deep Neural Network Accelerators Considering the Cost of Data Movement

付記する学位プログラム名: 京都大学卓越大学院プログラム「先端光・電子デバイス創成学」

Grantor dc:publisher

Kyoto University

Year dc:date.issued

2021

Author dc:creator

• Xu, Hongjie

• Low Power VLSI Design
• Deep Neural Network
• Parallel Processing
• Sparsity
• Hardware Accelerator

Statement dc:rights

• 1.Hongjie Xu, Jun Shiomi and Hidetoshi Onodera, Evaluation Metrics for the Cost of Data Movement in Deep Neural Network Acceleration, IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, 2021/06 2.Hongjie Xu, Jun Shiomi and Hidetoshi Onodera, MOSDA: On-chip Memory Optimized Sparse Deep Neural Network Accelerator with Efficient Index Matching, IEEE Open Journal of Circuits and Systems, 2020/12 3.Hongjie Xu, Jun Shiomi and Hidetoshi Onodera, On-chip Memory Optimized CNN Accelerator with Efficient Partial-sum Accumulation, The 30th edition of the ACM Great Lakes Symposium on VLSI (GLSVLSI), 2020/09 4.Hongjie Xu, Jun Shiomi, Tohru Ishihara and Hidetoshi Onodera, On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing, IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, vol E102-A, no 12, pp. 1741-1750, 2019/12 5.Hongjie Xu, Jun Shiomi, Tohru Ishihara, and Hidetoshi Onodera, Maximizing Energy Efficiency of On-Chip Caches Exploiting Hybrid Memory Structure, 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 237 - 242, DOI: 10.1109/PATMOS.2018.8464141, 2018/07

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/2433/263786

OAI identifier oai:identifier

oai:repository.kulib.kyoto-u.ac.jp:2433/263786