{"id":{"repo_id":"kyoto","oai_identifier":"oai:repository.kulib.kyoto-u.ac.jp:2433/263786"},"canonical_url":"https://search.dev.ndltd.org/etd/kyoto/oai:repository.kulib.kyoto-u.ac.jp:2433/263786","repository":{"repo_id":"kyoto","name":"Kyoto University","base_url":"https://repository.kulib.kyoto-u.ac.jp/server/oai/request"},"display":{"title":"Energy-Efficient On-Chip Cache Architectures and Deep Neural Network Accelerators Considering the Cost of Data Movement","abstract":"付記する学位プログラム名: 京都大学卓越大学院プログラム「先端光・電子デバイス創成学」","abstract_html":"付記する学位プログラム名: 京都大学卓越大学院プログラム「先端光・電子デバイス創成学」","abstract_has_math":false,"creators":["Xu, Hongjie"],"institution":"Kyoto University","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":null,"school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2021,"date_issued":"2021-03-23","date_published":"2021-03-23","updated_at":"2026-07-24T02:48:01Z","subjects":["Low Power VLSI Design","Deep Neural Network","Parallel Processing","Sparsity","Hardware Accelerator"],"languages":["eng"],"rights":["1.Hongjie Xu, Jun Shiomi and Hidetoshi Onodera, Evaluation Metrics for the Cost of Data Movement in Deep Neural Network Acceleration, IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, 2021/06 2.Hongjie Xu, Jun Shiomi and Hidetoshi Onodera, MOSDA: On-chip Memory Optimized Sparse Deep Neural Network Accelerator with Efficient Index Matching, IEEE Open Journal of Circuits and Systems, 2020/12 3.Hongjie Xu, Jun Shiomi and Hidetoshi Onodera, On-chip Memory Optimized CNN Accelerator with Efficient Partial-sum Accumulation, The 30th edition of the ACM Great Lakes Symposium on VLSI (GLSVLSI), 2020/09 4.Hongjie Xu, Jun Shiomi, Tohru Ishihara and Hidetoshi Onodera, On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing, IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, vol E102-A, no 12, pp. 1741-1750, 2019/12 5.Hongjie Xu, Jun Shiomi, Tohru Ishihara, and Hidetoshi Onodera, Maximizing Energy Efficiency of On-Chip Caches Exploiting Hybrid Memory Structure, 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 237 - 242, DOI: 10.1109/PATMOS.2018.8464141, 2018/07"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2433/263786","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:creator","label":"Author","values":["Xu, Hongjie"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2021-06-17T03:15:04Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2021-06-17T03:15:04Z"]},{"key":"dc:date.issued","label":"Date","values":["2021-03-23"]},{"key":"dc:publisher","label":"Institution","values":["Kyoto University"]},{"key":"dc:type","label":"Dc Type","values":["doctoral thesis"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Low Power VLSI Design","Deep Neural Network","Parallel Processing","Sparsity","Hardware Accelerator"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["1.Hongjie Xu, Jun Shiomi and Hidetoshi Onodera, Evaluation Metrics for the Cost of Data Movement in Deep Neural Network Acceleration, IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, 2021/06 2.Hongjie Xu, Jun Shiomi and Hidetoshi Onodera, MOSDA: On-chip Memory Optimized Sparse Deep Neural Network Accelerator with Efficient Index Matching, IEEE Open Journal of Circuits and Systems, 2020/12 3.Hongjie Xu, Jun Shiomi and Hidetoshi Onodera, On-chip Memory Optimized CNN Accelerator with Efficient Partial-sum Accumulation, The 30th edition of the ACM Great Lakes Symposium on VLSI (GLSVLSI), 2020/09 4.Hongjie Xu, Jun Shiomi, Tohru Ishihara and Hidetoshi Onodera, On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing, IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, vol E102-A, no 12, pp. 1741-1750, 2019/12 5.Hongjie Xu, Jun Shiomi, Tohru Ishihara, and Hidetoshi Onodera, Maximizing Energy Efficiency of On-Chip Caches Exploiting Hybrid Memory Structure, 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 237 - 242, DOI: 10.1109/PATMOS.2018.8464141, 2018/07"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/2433/263786"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["付記する学位プログラム名: 京都大学卓越大学院プログラム「先端光・電子デバイス創成学」"]},{"key":"dc:title","label":"Title","values":["Energy-Efficient On-Chip Cache Architectures and Deep Neural Network Accelerators Considering the Cost of Data Movement"]}]}],"canonical_facts":{"dc:creator":["Xu, Hongjie"],"dc:date.accessioned":["2021-06-17T03:15:04Z"],"dc:date.available":["2021-06-17T03:15:04Z"],"dc:date.issued":["2021-03-23"],"dc:description":["付記する学位プログラム名: 京都大学卓越大学院プログラム「先端光・電子デバイス創成学」"],"dc:identifier.uri":["http://hdl.handle.net/2433/263786"],"dc:language.iso":["eng"],"dc:publisher":["Kyoto University"],"dc:rights":["1.Hongjie Xu, Jun Shiomi and Hidetoshi Onodera, Evaluation Metrics for the Cost of Data Movement in Deep Neural Network Acceleration, IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, 2021/06 2.Hongjie Xu, Jun Shiomi and Hidetoshi Onodera, MOSDA: On-chip Memory Optimized Sparse Deep Neural Network Accelerator with Efficient Index Matching, IEEE Open Journal of Circuits and Systems, 2020/12 3.Hongjie Xu, Jun Shiomi and Hidetoshi Onodera, On-chip Memory Optimized CNN Accelerator with Efficient Partial-sum Accumulation, The 30th edition of the ACM Great Lakes Symposium on VLSI (GLSVLSI), 2020/09 4.Hongjie Xu, Jun Shiomi, Tohru Ishihara and Hidetoshi Onodera, On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing, IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, vol E102-A, no 12, pp. 1741-1750, 2019/12 5.Hongjie Xu, Jun Shiomi, Tohru Ishihara, and Hidetoshi Onodera, Maximizing Energy Efficiency of On-Chip Caches Exploiting Hybrid Memory Structure, 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 237 - 242, DOI: 10.1109/PATMOS.2018.8464141, 2018/07"],"dc:subject":["Low Power VLSI Design","Deep Neural Network","Parallel Processing","Sparsity","Hardware Accelerator"],"dc:title":["Energy-Efficient On-Chip Cache Architectures and Deep Neural Network Accelerators Considering the Cost of Data Movement"],"dc:type":["doctoral thesis"]},"updated_at":"2026-07-24T02:48:01Z"}