Energy-Efficient On-Chip Cache Architectures and Deep Neural Network Accelerators Considering the Cost of Data Movement
type: CreativeWork
description: 付記する学位プログラム名: 京都大学卓越大学院プログラム「先端光・電子デバイス創成学」
abstract: 付記する学位プログラム名: 京都大学卓越大学院プログラム「先端光・電子デバイス創成学」
author: Xu, Hongjie
language: eng
keywords: Low Power VLSI Design, Deep Neural Network, Parallel Processing, Sparsity, Hardware Accelerator
date published: 2021-03-23
date modified: 2026-07-24T02:48:01Z
provider: Kyoto University
publisher: Networked Digital Library of Theses and Dissertations
type: WebPage
source organization: Kyoto University

PropertyValue
property ID: Handle
value: http://hdl.handle.net/2433/263786