A Hardware Implementation of a Coherent SOQPSK-TG Demodulator for FEC Applications

This thesis presents a hardware design of a coherent demodulator for shaped offset quadrature phase shift keying, telemetry group version (SOQPSK-TG) for use in forward error correction (FEC) applications. Implementation details for data sequence detection, symbol timing synchronization, carrier phase synchronization, and block recovery are described. This decision-directed demodulator is based on maximum likelihood principles, and is efficiently implemented by the soft output Viterbi algorithm (SOVA). The design is intended for use in a field-programmable gate array (FPGA). Simulation results of the demodulator's performance in the additive white Gaussian noise channel are compared with a Matlab reference model that is known to be correct. In addition, hardware-specific parameters are presented. Finally, suggestions for future work and improvements are discussed.

Grantor dc:publisher

University of Kansas

Year dc:date.issued

2011

Author dc:creator

• Rea Zanabria, Gino

Advisor dc:contributor.advisor

• Perrins, Erik

• Electrical engineering
• Demodulator
• Fec
• Fpga
• Hardware
• Implementation
• Soqpsk-tg

Statement dc:rights

• This item is protected by copyright and unless otherwise specified the copyright of this thesis/dissertation is held by the author.

Language dc:language.iso

en

Dc Identifier Other

http://dissertations.umi.com/ku:11339

OAI identifier oai:identifier

oai:kuscholarworks.ku.edu:1808/7644