{"id":{"repo_id":"ku","oai_identifier":"oai:kuscholarworks.ku.edu:1808/7644"},"canonical_url":"https://search.dev.ndltd.org/etd/ku/oai:kuscholarworks.ku.edu:1808/7644","repository":{"repo_id":"ku","name":"University of Kansas","base_url":"https://kuscholarworks.ku.edu/server/oai/request"},"display":{"title":"A Hardware Implementation of a Coherent SOQPSK-TG Demodulator for FEC Applications","abstract":"This thesis presents a hardware design of a coherent demodulator for shaped offset quadrature phase shift keying, telemetry group version (SOQPSK-TG) for use in forward error correction (FEC) applications. Implementation details for data sequence detection, symbol timing synchronization, carrier phase synchronization, and block recovery are described. This decision-directed demodulator is based on maximum likelihood principles, and is efficiently implemented by the soft output Viterbi algorithm (SOVA). The design is intended for use in a field-programmable gate array (FPGA). Simulation results of the demodulator's performance in the additive white Gaussian noise channel are compared with a Matlab reference model that is known to be correct. In addition, hardware-specific parameters are presented. Finally, suggestions for future work and improvements are discussed.","abstract_html":"This thesis presents a hardware design of a coherent demodulator for shaped offset quadrature phase shift keying, telemetry group version (SOQPSK-TG) for use in forward error correction (FEC) applications. Implementation details for data sequence detection, symbol timing synchronization, carrier phase synchronization, and block recovery are described. This decision-directed demodulator is based on maximum likelihood principles, and is efficiently implemented by the soft output Viterbi algorithm (SOVA). The design is intended for use in a field-programmable gate array (FPGA). Simulation results of the demodulator's performance in the additive white Gaussian noise channel are compared with a Matlab reference model that is known to be correct. In addition, hardware-specific parameters are presented. Finally, suggestions for future work and improvements are discussed.","abstract_has_math":false,"creators":["Rea Zanabria, Gino"],"institution":"University of Kansas","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":null,"school":null,"contributors":[],"advisors":["Perrins, Erik"],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-03-31","date_published":"2011-03-31","updated_at":"2026-07-24T02:46:40Z","subjects":["Electrical engineering","Demodulator","Fec","Fpga","Hardware","Implementation","Soqpsk-tg"],"languages":["en"],"rights":["This item is protected by copyright and unless otherwise specified the copyright of this thesis/dissertation is held by the author."],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["http://dissertations.umi.com/ku:11339"],"render_values":[{"text":"http://dissertations.umi.com/ku:11339","href":"http://dissertations.umi.com/ku:11339","code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/1808/7644","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Perrins, Erik"]},{"key":"dc:creator","label":"Author","values":["Rea Zanabria, Gino"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2011-06-21T16:35:34Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2011-06-21T16:35:34Z"]},{"key":"dc:date.issued","label":"Date","values":["2011-03-31"]},{"key":"dc:publisher","label":"Institution","values":["University of Kansas"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Electrical engineering","Demodulator","Fec","Fpga","Hardware","Implementation","Soqpsk-tg"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["This item is protected by copyright and unless otherwise specified the copyright of this thesis/dissertation is held by the author."]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["http://dissertations.umi.com/ku:11339"]},{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/1808/7644"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["This thesis presents a hardware design of a coherent demodulator for shaped offset quadrature phase shift keying, telemetry group version (SOQPSK-TG) for use in forward error correction (FEC) applications. Implementation details for data sequence detection, symbol timing synchronization, carrier phase synchronization, and block recovery are described. This decision-directed demodulator is based on maximum likelihood principles, and is efficiently implemented by the soft output Viterbi algorithm (SOVA). The design is intended for use in a field-programmable gate array (FPGA). Simulation results of the demodulator's performance in the additive white Gaussian noise channel are compared with a Matlab reference model that is known to be correct. In addition, hardware-specific parameters are presented. Finally, suggestions for future work and improvements are discussed."]},{"key":"dc:title","label":"Title","values":["A Hardware Implementation of a Coherent SOQPSK-TG Demodulator for FEC Applications"]}]}],"canonical_facts":{"dc:contributor.advisor":["Perrins, Erik"],"dc:creator":["Rea Zanabria, Gino"],"dc:date.accessioned":["2011-06-21T16:35:34Z"],"dc:date.available":["2011-06-21T16:35:34Z"],"dc:date.issued":["2011-03-31"],"dc:description.abstract":["This thesis presents a hardware design of a coherent demodulator for shaped offset quadrature phase shift keying, telemetry group version (SOQPSK-TG) for use in forward error correction (FEC) applications. Implementation details for data sequence detection, symbol timing synchronization, carrier phase synchronization, and block recovery are described. This decision-directed demodulator is based on maximum likelihood principles, and is efficiently implemented by the soft output Viterbi algorithm (SOVA). The design is intended for use in a field-programmable gate array (FPGA). Simulation results of the demodulator's performance in the additive white Gaussian noise channel are compared with a Matlab reference model that is known to be correct. In addition, hardware-specific parameters are presented. Finally, suggestions for future work and improvements are discussed."],"dc:identifier.other":["http://dissertations.umi.com/ku:11339"],"dc:identifier.uri":["http://hdl.handle.net/1808/7644"],"dc:language.iso":["en"],"dc:publisher":["University of Kansas"],"dc:rights":["This item is protected by copyright and unless otherwise specified the copyright of this thesis/dissertation is held by the author."],"dc:subject":["Electrical engineering","Demodulator","Fec","Fpga","Hardware","Implementation","Soqpsk-tg"],"dc:title":["A Hardware Implementation of a Coherent SOQPSK-TG Demodulator for FEC Applications"],"dc:type":["Thesis"]},"updated_at":"2026-07-24T02:46:40Z"}