Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 131 for “"Field-Programmable Gate Array (FPGA)"”.
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Neural network field programmable gate array (FPGA) controllers for reconfigurable antennas
… the advantages of both Neural Networks (NN) and Field Programmable Gate Arrays (FPGAs) to overcome this dilemma. In this work, the methodology of modeling of reconfigurable antennas using neural network embedded on an FPGA board is presented. This work shows a new approach of modeling …
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Tutorial on designing and implementing a direct digital synthesizer (DDS) on a field programmable gate array (FPGA)
… on designing and implementing a DDS on an FPGA using Xilinx’s ISE software. The thesis also examines the final results and shows the unwanted spurs that are generated. Since this is purely a digital design, it does not implement a digital-to-analog converter (DAC) or a low-pass filter. …
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Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA)
… the direct digital synthesizer (DDS) and investigate the signal integrity issues associated with the DDS design. In order to minimize the size of the lookup table to save hardware and lower the power consumption, we normally truncate the phase word output from the phase accumulator in the …
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Modeling, simulation and implementation of a non-coherent binary-frequency-shift-keying (BFSK) receiver-transmitter into a field programmable gate array (FPGA)
This thesis presents the use of a field programmable gate array (FPGA) to implement a non-coherent binary-frequency-shift-keyed receiver-transmitter (BFSK-RT) that simulates the modulation of the SINCGARS radio, the RT-1523C. An FPGA successfully, and with very few resources, implemented the …
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Field-programmable gate-array (FPGA) implementation of low-density parity-check (LDPC) decoder in digital video broadcasting - second generation satellite (DVB-S2)
… In this thesis, the design and architecture of a FPGA implementation of an LDPC decoder for the DVB-S2 standard are presented. The decoder architecture is an improvement over others that are published in the current literature. Novel algorithms are devised to use a memory mapping scheme that …
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A Design Assembly Technique for FPGA Back-End Acceleration
… performed in a day, thus risking to restrict Field-Programmable Gate Array (FPGA) adaptation in modern computing platforms. This work presents an FPGA development paradigm that exploits logic variance and hierarchy as a means to increase FPGA productivity. The practical tasks of logic …
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Artificial Frequency Match Neuron Implemented with Digital Logic
… simulator and successfully implemented on a Field Programmable Gate Array (FPGA) to prove its viability.</p>
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FPGA-based architectures for next generation communications networks
… doctorate concerns the application of Field Programmable Gate Array (FPGA) technology to some of the challenges faced in the design of next generation communications networks. The growth and convergence of such networks has fuelled demand for higher bandwidth systems, and a requirement …
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Reconfigurable logic test methodologies for ISDN
… addresses a different aspect of ISDN testing. Field programmable gate array (FPGA) technology was employed to facilitate the development. The design and development work produced a hardware platform that could be reconfigured to provide the test features associated with each project. The three …
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FPGA-based digital phase-locked loop analysis and implementation
… for future communication research projects. Field Programmable Gate Array (FPGA) technology is used for all digital signal processing tasks. A Direct Digital Synthesizer (DDS) is used to synthesize analog output, the frequency of which is controlled digitally by the FPGA. This system is …
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A Hardware Implementation of a Coherent SOQPSK-TG Demodulator for FEC Applications
… (SOVA). The design is intended for use in a field-programmable gate array (FPGA). Simulation results of the demodulator's performance in the additive white Gaussian noise channel are compared with a Matlab reference model that is known to be correct. In addition, hardware-specific parameters …
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Enhancing FPGA Synthesis for Space Applications: Performance Evaluation of ScaleHLS in the ADAPT Project
<p>This thesis investigates the application of ScaleHLS, a high-level synthesis (HLS) tool, to enhance Field-Programmable Gate Array (FPGA) synthesis for space applications, with a focus on the Antarctic Demonstrator Advanced Particle-astrophysics Telescope (ADAPT) project. The study explores how …
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A field programmable gate array based software defined radio design for the space environment
… signal output. The design is based on a Field Programmable Gate Array (FPGA), which is chosen for its reprogrammability, flexibility, and our ability to introduce fault tolerance into the design. Software design tools allowed programming to be done at a high level, thereby allowing more …
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Manta: An In-Situ Debugging Tool for Programmable Hardware
… considerable effort accommodating toolchains for Field Programmable Gate Array (FPGA) development, which include utilities for debugging logic on the FPGA itself. As an alternative, this work proposes Manta, a lightweight, modular, platform-independent, and intuitive tool for debugging digital …
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Investigation of Non-Traditional Applications of the Physical Level in Reconfigurable Computing
… are proposed that utilize low-level knowledge of Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) design processes to enable additional research avenues. In order to accomplish these projects, Tools for Open Reconfigurable Computing (TORC) is utilized to …
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JHDLBits: An Open-Source Model for FPGA Design Automation
Today's Field Programmable Gate Array (FPGA) research community could use an extensible tool flow enabling designers to examine new algorithms and new methods of interacting with FPGA configurations. One such flow is JHDLBits, which integrates two prominent FPGA design environments: JHDL and JBits. …
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PRIVACY-AWARE AND HARDWARE-BASED ACCLERATION AUTHENTICATION SCHEME FOR INTERNET OF DRONES
… is a problem that I choose to tackle using a Field Programmable Gate Array (FPGA) that accelerates the k-Nearest Neighbor (kNN) encryption algorithm making it a hardware component. This will allow me to synthesis and implement the three parts of my privacy-aware and hardware-based …
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Implementation of Orthogonal Frequency Division Multiplexing with FPGA
… Frequency Division Multiplexing system on field-programmable gate array (FPGA). The major components of an OFDM system include a modulator, an N-input inverse Fast Fourier Transform (IFFT), two root raised cosine filters (RRC filter), an N-input Fast Fourier Transform (FFT), and a …
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Verification and Configuration of a Run-Time Reconfigurable Custom Computing Integrated Circuit for DSP Applications
… activity surrounding CCMs has centered around Field-Programmable Gate Array (FPGA) technology and rapid prototyping applications. While higher performance has been a concern in some applications, the solutions are limited by the relatively small FPGA bandwidth, density and throughput. This …
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Framework for Hardware Agility on FPGAs
… needs to evolve and adapt to the demands. Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit, General Purpose Processor, and System on Chip are the preferred devices for solving computational problems. Each of these platforms has its own specific advantages and …
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