Network Attached Hardware Block (NAHB) Framework

Modern FPGA (Field Programmable Gate Array) systems have significant data processing capabilities but limited memory and storage. This thesis creates a common framework by which multiple logic modules within one or more FPGAs may offload data to and access data from connected resources such as a server or other FPGA/SoC system on a network. This implementation, which will be called the Network Attached Hardware Block (NAHB) framework is entirely hardware based and maintains high throughput and low latency without a software/firmware network stack. The proposed protocol may be utilized across various physical layer types, but will be designed to function on a Gigabit Ethernet network as an example. Such a common framework allows for robust and simplified development of multi-FPGA systems that can take advantage of local or network connected resources. This framework shares a network connection between multiple endpoints within a device and will allow for arbitration between endpoints.

Name thesis:degree_name

Master of Science

Level thesis:degree_level

Masters

Discipline thesis:degree_discipline

Computer and Systems Engineering

Grantor

University of Houston

Year dc:date.issued

2018

Author dc:creator

• Rozenberg, Gennadiy

Advisor dc:contributor.advisor

• Chen, Yuhua

Committee members dc:contributor.committeemember

• Wolfe, John C.
• Zagozdzon-Wosik, Wanda
• Vipulanandan, Cumaraswamy

• FPGA
• NAHB
• Ethernet
• Networks

Statement dc:rights

• The author of this work is the copyright owner. UH Libraries and the Texas Digital Library have their permission to store and provide access to this work. Further transmission, reproduction, or presentation of this work is prohibited except with permission of the author(s).

Language dc:language.iso

eng

Handle dc:identifier.uri

https://hdl.handle.net/10657/5838

OAI identifier oai:identifier

oai:uh-ir.tdl.org:10657/5838