{"id":{"repo_id":"houston","oai_identifier":"oai:uh-ir.tdl.org:10657/5838"},"canonical_url":"https://search.dev.ndltd.org/etd/houston/oai:uh-ir.tdl.org:10657/5838","repository":{"repo_id":"houston","name":"University of Houston","base_url":"https://uh-ir.tdl.org/server/oai/request"},"display":{"title":"Network Attached Hardware Block (NAHB) Framework","abstract":"Modern FPGA (Field Programmable Gate Array) systems have significant data processing capabilities but limited memory and storage. This thesis creates a common framework by which multiple logic modules within one or more FPGAs may offload data to and access data from connected resources such as a server or other FPGA/SoC system on a network. This implementation, which will be called the Network Attached Hardware Block (NAHB) framework is entirely hardware based and maintains high throughput and low latency without a software/firmware network stack. The proposed protocol may be utilized across various physical layer types, but will be designed to function on a Gigabit Ethernet network as an example. Such a common framework allows for robust and simplified development of multi-FPGA systems that can take advantage of local or network connected resources. This framework shares a network connection between multiple endpoints within a device and will allow for arbitration between endpoints.","abstract_html":"Modern FPGA (Field Programmable Gate Array) systems have significant data processing capabilities but limited memory and storage. This thesis creates a common framework by which multiple logic modules within one or more FPGAs may offload data to and access data from connected resources such as a server or other FPGA/SoC system on a network. This implementation, which will be called the Network Attached Hardware Block (NAHB) framework is entirely hardware based and maintains high throughput and low latency without a software/firmware network stack. The proposed protocol may be utilized across various physical layer types, but will be designed to function on a Gigabit Ethernet network as an example. Such a common framework allows for robust and simplified development of multi-FPGA systems that can take advantage of local or network connected resources. This framework shares a network connection between multiple endpoints within a device and will allow for arbitration between endpoints.","abstract_has_math":false,"creators":["Rozenberg, Gennadiy"],"institution":"University of Houston","degree_name":"Master of Science","degree_level":"Masters","degree_discipline":"Computer and Systems Engineering","degree_department":null,"school":null,"contributors":[],"advisors":["Chen, Yuhua"],"committee_chairs":[],"committee_members":["Wolfe, John C.","Zagozdzon-Wosik, Wanda","Vipulanandan, Cumaraswamy"],"year":2018,"date_issued":"2018-12","date_published":"2018-12","updated_at":"2026-07-24T02:33:01Z","subjects":["FPGA","NAHB","Ethernet","Networks"],"languages":["eng"],"rights":["The author of this work is the copyright owner. UH Libraries and the Texas Digital Library have their permission to store and provide access to this work. Further transmission, reproduction, or presentation of this work is prohibited except with permission of the author(s)."],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/10657/5838","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Chen, Yuhua"]},{"key":"dc:contributor.committeemember","label":"Committee Member","values":["Wolfe, John C.","Zagozdzon-Wosik, Wanda","Vipulanandan, Cumaraswamy"]},{"key":"dc:creator","label":"Author","values":["Rozenberg, Gennadiy"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2020-01-07T04:03:33Z"]},{"key":"dc:date.issued","label":"Date","values":["2018-12"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Computer and Systems Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Masters"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master of Science"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Houston"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["FPGA","NAHB","Ethernet","Networks"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["The author of this work is the copyright owner. UH Libraries and the Texas Digital Library have their permission to store and provide access to this work. Further transmission, reproduction, or presentation of this work is prohibited except with permission of the author(s)."]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["https://hdl.handle.net/10657/5838"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["Modern FPGA (Field Programmable Gate Array) systems have significant data processing capabilities but limited memory and storage. This thesis creates a common framework by which multiple logic modules within one or more FPGAs may offload data to and access data from connected resources such as a server or other FPGA/SoC system on a network. This implementation, which will be called the Network Attached Hardware Block (NAHB) framework is entirely hardware based and maintains high throughput and low latency without a software/firmware network stack. The proposed protocol may be utilized across various physical layer types, but will be designed to function on a Gigabit Ethernet network as an example. Such a common framework allows for robust and simplified development of multi-FPGA systems that can take advantage of local or network connected resources. This framework shares a network connection between multiple endpoints within a device and will allow for arbitration between endpoints."]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Network Attached Hardware Block (NAHB) Framework"]}]}],"canonical_facts":{"dc:contributor.advisor":["Chen, Yuhua"],"dc:contributor.committeemember":["Wolfe, John C.","Zagozdzon-Wosik, Wanda","Vipulanandan, Cumaraswamy"],"dc:creator":["Rozenberg, Gennadiy"],"dc:date.accessioned":["2020-01-07T04:03:33Z"],"dc:date.issued":["2018-12"],"dc:description.abstract":["Modern FPGA (Field Programmable Gate Array) systems have significant data processing capabilities but limited memory and storage. This thesis creates a common framework by which multiple logic modules within one or more FPGAs may offload data to and access data from connected resources such as a server or other FPGA/SoC system on a network. This implementation, which will be called the Network Attached Hardware Block (NAHB) framework is entirely hardware based and maintains high throughput and low latency without a software/firmware network stack. The proposed protocol may be utilized across various physical layer types, but will be designed to function on a Gigabit Ethernet network as an example. Such a common framework allows for robust and simplified development of multi-FPGA systems that can take advantage of local or network connected resources. This framework shares a network connection between multiple endpoints within a device and will allow for arbitration between endpoints."],"dc:format.mimetype":["application/pdf"],"dc:identifier.uri":["https://hdl.handle.net/10657/5838"],"dc:language.iso":["eng"],"dc:rights":["The author of this work is the copyright owner. UH Libraries and the Texas Digital Library have their permission to store and provide access to this work. Further transmission, reproduction, or presentation of this work is prohibited except with permission of the author(s)."],"dc:subject":["FPGA","NAHB","Ethernet","Networks"],"dc:title":["Network Attached Hardware Block (NAHB) Framework"],"thesis:degree_discipline":["Computer and Systems Engineering"],"thesis:degree_level":["Masters"],"thesis:degree_name":["Master of Science"],"thesis:institution_name":["University of Houston"]},"updated_at":"2026-07-24T02:33:01Z"}