Comprehensive variation-aware aging simulator for logic timing and SRAM stability

This research developed a framework which analyzes circuit-level reliability and evaluates the lifetimes of complex systems like state-of-art microprocessors. The novelty of the proposed work lies on its statistical timing analyzer and the ability to handle the combined effect of a variety of front-end-of-line (FEOL) wearout mechanisms, while including both the manufacturing process variability and the real-time uncertainties in workload and ambient conditions like operating temperature and IR drops. Overall, the proposed framework presents the correlation between circuit performance (speed) and circuit lifetime, which enables circuit designers to avoid excessive guard-banding, by using a better understood reliability budget to achieve higher performance.

Level thesis:degree_level

Doctoral

Department dc:contributor.department

Electrical and Computer Engineering

Grantor dc:publisher

Georgia Institute of Technology

Year dc:date.issued

2017

Author dc:creator

• Liu, Taizhi

Advisor dc:contributor.advisor

• Milor, Linda S.

Committee members dc:contributor.committeemember

• Chatterjee, Abhijit
• Lim, Sung Kyu
• Lu, Jye-Chyi
• Naeemi, Azad

• Microelectronics
• Statistical timing analysis
• SRAM stability
• Data cache
• Circuit aging
• BTI
• HCI
• GOBD

Language dc:language.iso

en_US

Handle dc:identifier.uri

http://hdl.handle.net/1853/58287

OAI identifier oai:identifier

oai:repository.gatech.edu:1853/58287