{"id":{"repo_id":"gatech","oai_identifier":"oai:repository.gatech.edu:1853/58287"},"canonical_url":"https://search.dev.ndltd.org/etd/gatech/oai:repository.gatech.edu:1853/58287","repository":{"repo_id":"gatech","name":"Georgia Tech","base_url":"https://repository.gatech.edu/server/oai/request"},"display":{"title":"Comprehensive variation-aware aging simulator for logic timing and SRAM stability","abstract":"This research developed a framework which analyzes circuit-level reliability and evaluates the lifetimes of complex systems like state-of-art microprocessors. The novelty of the proposed work lies on its statistical timing analyzer and the ability to handle the combined effect of a variety of front-end-of-line (FEOL) wearout mechanisms, while including both the manufacturing process variability and the real-time uncertainties in workload and ambient conditions like operating temperature and IR drops. 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