Lattice reduction for MIMO detection: from theoretical analysis to hardware realization

The objective of the dissertation research is to understand the complex interaction between the algorithm and hardware aspects of symbol detection that is enhanced by lattice reduction (LR) preprocessing for wireless MIMO communication systems. The motivation for this work stems from the need to improve the bit-error-rate performance of conventional, low-complexity detectors while simultaneously exhibiting considerably reduced complexity when compared to the optimal method, maximum likelihood detection. Specifically, we first develop an understanding of the complex Lenstra-Lenstra-Lovász (CLLL) LR algorithm from a hardware perspective. This understanding leads to both algorithm modifications that reduce the required complexity and hardware architectures that are specifically optimized for the CLLL algorithm. Finally, we integrate this knowledge with an understanding of LR-aided MIMO symbol detection in a highly-correlated wireless environment, resulting in a joint LR/symbol detection algorithm that maps seamlessly to hardware. Hence, this dissertation forms the foundation for the adoption of lattice reduction algorithms in practical, high-throughput wireless MIMO communications systems.

Department dc:contributor.department

Electrical and Computer Engineering

Grantor dc:publisher

Georgia Institute of Technology

Year dc:date.issued

2011

Author dc:creator

• Gestner, Brian Joseph

Advisor dc:contributor.advisor

• Anderson, David V.

Committee members dc:contributor.committeemember

• Barry, John
• Santosh Pande
• Yalamanchili, Sudhakar
• Xiaoli Ma

• MIMO
• Wireless
• Lattice reduction
• VLSI
• Hardware
• FPGA

Handle dc:identifier.uri

http://hdl.handle.net/1853/39591

OAI identifier oai:identifier

oai:repository.gatech.edu:1853/39591