Back to results

University of Cambridge

Energy Proportional Future Chip-to-chip Computing Interconnect Designs

Abstract

dc:description.abstract

Multichiplet systems can be utilised to build a flexible, reconfigurable board-level computing platform with enhanced resource consumption and energy efficiency. Optical interconnects feature high IO capacity, distance-independent energy consumption, and low-delay connection. Optical linking fabric allows comprehensive customization of system architecture and resource allocation, which is not possible with electrical approaches. However, current optical technologies create static power overheads that reduce performance and dynamic power. This thesis offers and assesses unique architectural approaches for power-efficient multichiplet board-level optical connection usage. First, we recommend "unorthodox" UMA multi-chiplet architectures for on-board computers. We show it is only viable with optical interconnects, and simulations show it can improve execution speed and energy efficiency for a variety of workloads. We make our own simulation systems to evaluate the design trade-offs and rules for the network utilization methods are theoretically derived while the energy-delay products are investigated under various launch conditions. Then, we offer 'RENU,' a unique on-board optical interconnect control technique assessed with wavelength and spatial optical switching fabric. RENU maximises utilisation by rearranging interconnects depending on application network traces. Energy consumption is reduced, especially in low-use paradigms, compared to state-of-the-art. We then propose 'Min-ORUM', an online utilisation maximisation technique that reduces energy consumption for a variety of applications. Finally, we present 'SO-RA', a novel laser distribution control system using sophisticated SOA-based switch matrics. It reduces static power losses by reconfiguring in nanosecond time.

Degree

thesis:*
Name dc:type.qualificationname
Doctor of Philosophy (PhD)
Level dc:type.qualificationlevel
Doctoral
Grantor dc:publisher.institution
University of Cambridge
Year dc:date.issued
2023

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Sharma, Arastu
Advisors dc:contributor.advisor
  • Penty, Richard
  • White, Ian

Subjects

dc:subject × 28

Rights

dc:rights
Language dc:language
eng

Identifiers

dc:identifier.*
DOI dc:identifier.doi
https://doi.org/10.17863/CAM.100567
OAI identifier oai:identifier
oai:www.repository.cam.ac.uk:1810/355662

Chain of custody

source
Harvested from
Cambridge University
Base URL
api.repository.cam.ac.uk/server/oai/request
Last updated
2026-07-24
Source record
OAI-PMH GetRecord
citation

Sharma, Arastu. Energy Proportional Future Chip-to-chip Computing Interconnect Designs. Doctoral thesis, University of Cambridge, 2023. https://doi.org/10.17863/CAM.100567