Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 25 for “"Chip-to-chip"”.
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Energy Proportional Future Chip-to-chip Computing Interconnect Designs
Multichiplet systems can be utilised to build a flexible, reconfigurable board-level computing platform with enhanced resource consumption and energy efficiency. Optical interconnects feature high IO capacity, distance-independent energy consumption, and low-delay connection. Optical linking fabric …
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Circuit and Modeling Solutions for High-Speed Chip-to-Chip Communication
… noise and timing jitter across high-speed chip-to-chip interconnects. Channel equalization and associated tuning schemes have been developed to target the distinct characteristics and signal degradation exhibited in the clock and data signals of multi-Gigabit/second digital communication …
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The integration of InP /InGaAsP ridge waveguide structures with dielectric waveguides on silicon
Chip-to-chip optical interconnect technology, which is being explored as a potential replacement for copper chip-to-chip interconnects at data transmission rates exceeding 10 Gb/s, is one of several technologies that could be enabled by the monolithic integration of III-V optoelectronic devices on …
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Reversible concentric ring microfluidic interconnects
A reversible, Chip-to-Chip microfluidic interconnect was designed for use in high temperature, high pressure applications such as chemical microreactor systems. The interconnect uses two sets of concentric, interlocking rings with trapezoidal cross sections to form a fluid seal without the use of …
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Design, Analysis and Simulation of Optoelectronic Integrated Circuits (Oeics) and Subsystems
Over the past several decades, the field of optoelectronics has grown from a few laboratory experiments into an entire industry; in particular, because of the superior transmission characteristics of optical fiber, optical communications has become a field of its own. While its most easily …
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Analysis of variation in on-chip waveguide distribution schemes and optical receiver circuits
… has emerged as a possible alternative to electrical interconnect at chip-to-chip and on-chip length scales because of its potential to overcome power, delay, and bandwidth limitations of traditional electrical interconnect. This thesis examines the issues of variation involved in the …
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DETECTING DELAY ANOMALIES INTRODUCED BY HARDWARE TROJANS USING CHIP AVERAGING AND AN ON-CHIP HIGH RESOLUTION EMBEDDED TEST STRUCTURE
… delays are measured using a high resolution on-chip embedded test structure called a time-to-digital converter (TDC) that provides approx. 25 ps of timing resolution. A calibration method for the TDC as well as a chip-averaging technique are demonstrated to nearly eliminate chip-to-chip and …
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Scalable multi-access flash store for Big Data analytics
For many "Big Data" applications, the limiting factor in performance is often the transportation of large amount of data from hard disks to where it can be processed, i.e. DRAM. In this work we examine an architecture for a scalable distributed flash store which aims to overcome this limitation in …
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Channel-and-circuits aware, energy-efficient coding for high speed links
Throughput and energy-efficiency of high-speed chip-to-chip interconnects present critical bottlenecks in a whole range of important applications, from processor-memory interfaces, to network routers. These links currently rely solely on complex equalization techniques to maintain the bit error …
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Design of a clock and data recovery circuit in 65 nm technology
As semiconductor fabrication technology develops, the demand for higher transmission data rates constantly increases; thus there is an urgent need for a power-efficient, robust and broad bandwidth chip-to-chip communication method. A lot of work has been done to address this issue as researchers …
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Model predictive control equalization for high-speed IO links
The demand for bandwidth in chip-to-chip communication has been increasing as the industry demands higher quantity and quality of information. Serial links provide a suitable architecture for this kind of transmission, because of speed, power and area limitations on parallel links. However, due to …
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Photonic crystal emitters in heterogeneously bonded membranes
Photonic crystal (PhC) membrane lasers are good candidates for future photonic integrated circuit applications, including chip-to-chip and on-chip optical interconnects. This is due to their small size, lithographically tunable emission wavelength, and potential for low power operation. In order to …
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Power-efficient high-speed interface circuit techniques
<p>Inter- and intra-chip connections have become the new challenge to enable the scaling of computing systems, ranging from mobile devices to high-end servers. Demand for aggregate I/O bandwidth has been driven by applications including high-speed ethernet, backplane micro-servers, memory, …
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Photonic Integrated Circuit Packaging Using Silicon Based Optical Interconnects
… interconnections reach their physical limit, optoelectronic packaging solutions are a critical bottleneck in the effort to seamlessly integrate silicon photonic devices - a technology capable of handling high data rates for next generation data center telecom applications. In this thesis, novel …
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Channel coding for high speed links
… of channel coding for high-speed backplane or chip-to-chip interconnects, referred to as the high-speed links. Although both power-constrained and bandwidth-limited, the high-speed links need to support data rates in the Gbps range at low error probabilities. Modeling the high-speed link as a …
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Modelling and applications of MOS varactors for high-speed CMOS clock and data recovery
… a wide range from wireline long-haul networks to chip-to-chip and backplane communications. In this dissertation, our focus is on the modelling, design and analysis of devices and circuits used in this versatile system in CMOS technology. Of these blocks, we have identified the …
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Design and modelling of clock and data recovery integrated circuit in 130 nm CMOS technology for 10 Gb/s serial data communications
… modeling of an asynchronous serial link based chip to chip communication system incorporating the proposed concept. The proposed design was implemented and fabricated using the 130 nm CMOS technology offered by UMC (United Microelectronics Corporation). Different PLL-based CDR circuits …
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Design space exploration of photonic interconnects
As processors scale deep into the multi-core and many-core regimes, bandwidth and energy-efficiency of the on-die interconnect network have become paramount design issues. Recognizing potential limits of electrical interconnects, emerging nanophotonic integration has been recently proposed as a …
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Efficient Light Coupling Techniques for Integrated Photonics
… not exist, in most cases, light is still coupled to photonic chips from an external source (i.e. off-chip lasers) through single mode optical fibers (SMF). In this thesis, my investigations are focused on the problem of efficient light coupling to nano-photonic devices of different types. I …
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High-Speed Low-Voltage Line Driver for SerDes Applications
The driving factor behind this research was to design & develop a line driver capable of meeting the demanding specifications of the next generation of SerDes devices. In this thesis various line driver topologies were analysed to identify a topology suited for a high-speed low-voltage operating …
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