Proposta de implementação dos algoritmos de hash MD5 e SHA-1 em hardware reconfigurável

This work proposes two Application Specific System Processor (ASSP), one to the MD5 algorithm and other to the SHA-1 algorithm implemented on Field Programmable Gate Array (FPGA) Xilinx Virtex 6 xc6vlx240t-1ff1156. The throughput and the occupied area were analyzed for several implementations on parallel instances of those algorithms. The results showed that the hardware proposed for MD5 achieved a better throughput than those found in published articles and it was possible to implement 320 instances of the algorithm in a single FPGA. For the SHA-1 algorithm the throughput and the area occupied by the internal circuits on the chip were also surprising when compared with other papers. Several applications such as password recovery, password validation, and high volume data integrity checking can be performed efficiently and quickly with an ASSP for MD5 and SHA-1. This work also presents a comparative analysis of the energy consumption associated with execution of the MD5 and SHA-1 algorithms for three different hardware platforms, a microprocessor (µP) of 8 bits and 32 bits and the specific application hardware designed for each algorithm. Results of consumption estimation from the processing time (measured in the laboratory) show that the use of dedicated hardware presents significant gains in energy savings.

Grantor

Brasil

Year dc:date.issued

2018

Author dc:creator

• Santos Júnior, Carlos Eduardo de Barros

Advisor dc:contributor.advisor

• Fernandes, Marcelo Augusto Costa

• Hash
• FPGA
• MD5
• SHA-1
• Processamento

Statement dc:rights

• Acesso Aberto

Language dc:language

por

Repository record dc:identifier.uri

https://repositorio.ufrn.br/jspui/handle/123456789/25779

OAI identifier oai:identifier

oai:repositorio.ufrn.br:123456789/25779