CAD Tool Design for NCL and MTNCL Asynchronous Circuits

<p>This thesis presents an implementation of a method developed to readily convert Boolean designs into an ultra-low power asynchronous design methodology called MTNCL, which combines multi-threshold CMOS (MTCMOS) with NULL Convention Logic (NCL) systems. MTNCL provides the leakage power advantages of an all high-Vt implementation with a reasonable speed penalty compared to the all low-Vt implementation, and has negligible area overhead. The proposed tool utilizes industry-standard CAD tools. This research also presents an Automated Gate-Level Pipelining with Bit-Wise Completion (AGLPBW) method to maximize throughput of delay-insensitive full-word pipelined NCL circuits. These methods have been integrated into the Mentor Graphics and Synopsis CAD tools, using a C-program, which performs the majority of the computations, such that the method can be easily ported to other CAD tool suites. Both methods have been successfully tested on circuits, including a 4-bit × 4-bit multiplier, an unsigned Booth2 multiplier, and a 4-bit/8-operation arithmetic logic unit (ALU)</p>

Name thesis:degree_name

Master of Science in Electrical Engineering (MSEE)

Level thesis:degree_level

Thesis

Year dc:date.available

2013

Author dc:creator

• Pillai, Vijay Mani

Advisor dc:contributor.advisor

• Smith, Scott C.

Contributors dc:contributor

• Brown, Randy L.
• Mantooth, H. Alan

• Applied sciences
• Asynchronous circuits
• Bit-wise ncl
• Bolean to mtncl
• Cad tool design
• Mtncl
• Ncl
• Digital Circuits
• VLSI and Circuits, Embedded and Hardware Systems

Repository record dc:identifier

https://scholarworks.uark.edu/etd/829

OAI identifier oai:identifier

oai:scholarworks.uark.edu:etd-1828