This thesis presents an implementation of a method developed to readily convert Boolean designs into an ultra-low power asynchronous design methodology called MTNCL, which combines multi-threshold CMOS (MTCMOS) with NULL Convention Logic (NCL) systems. MTNCL provides the leakage power advantages of an all high-Vt implementation with a reasonable speed penalty compared to the all low-Vt implementation, and has negligible area overhead. The proposed tool utilizes industry-standard CAD tools. This research also presents an Automated Gate-Level Pipelining with Bit-Wise Completion (AGLPBW) method to maximize throughput of delay-insensitive full-word pipelined NCL circuits. These methods have been integrated into the Mentor Graphics and Synopsis CAD tools, using a C-program, which performs the majority of the computations, such that the method can be easily ported to other CAD tool suites. Both methods have been successfully tested on circuits, including a 4-bit × 4-bit multiplier, an unsigned Booth2 multiplier, and a 4-bit/8-operation arithmetic logic unit (ALU)
","abstract_html":"<p>This thesis presents an implementation of a method developed to readily convert Boolean designs into an ultra-low power asynchronous design methodology called MTNCL, which combines multi-threshold CMOS (MTCMOS) with NULL Convention Logic (NCL) systems. MTNCL provides the leakage power advantages of an all high-Vt implementation with a reasonable speed penalty compared to the all low-Vt implementation, and has negligible area overhead. The proposed tool utilizes industry-standard CAD tools. This research also presents an Automated Gate-Level Pipelining with Bit-Wise Completion (AGLPBW) method to maximize throughput of delay-insensitive full-word pipelined NCL circuits. These methods have been integrated into the Mentor Graphics and Synopsis CAD tools, using a C-program, which performs the majority of the computations, such that the method can be easily ported to other CAD tool suites. Both methods have been successfully tested on circuits, including a 4-bit × 4-bit multiplier, an unsigned Booth2 multiplier, and a 4-bit/8-operation arithmetic logic unit (ALU)</p>","abstract_has_math":false,"creators":["Pillai, Vijay Mani"],"institution":null,"degree_name":"Master of Science in Electrical Engineering (MSEE)","degree_level":"Thesis","degree_discipline":null,"degree_department":null,"school":null,"contributors":["Brown, Randy L.","Mantooth, H. Alan"],"advisors":["Smith, Scott C."],"committee_chairs":[],"committee_members":[],"year":2013,"date_issued":"2013-08-01T07:00:00Z","date_published":"2013-08-01T07:00:00Z","updated_at":"2026-07-24T00:59:58Z","subjects":["Applied sciences","Asynchronous circuits","Bit-wise ncl","Bolean to mtncl","Cad tool design","Mtncl","Ncl","Digital Circuits","VLSI and Circuits, Embedded and Hardware Systems"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://scholarworks.uark.edu/etd/829","outbound_label":"Repository record","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Brown, Randy L.","Mantooth, H. Alan"]},{"key":"dc:contributor.advisor","label":"Advisor","values":["Smith, Scott C."]},{"key":"dc:creator","label":"Author","values":["Pillai, Vijay Mani"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2013"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2017-09-29T07:00:00Z"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master of Science in Electrical Engineering (MSEE)"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Applied sciences","Asynchronous circuits","Bit-wise ncl","Bolean to mtncl","Cad tool design","Mtncl","Ncl","Digital Circuits","VLSI and Circuits, Embedded and Hardware Systems"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://scholarworks.uark.edu/etd/829"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["This thesis presents an implementation of a method developed to readily convert Boolean designs into an ultra-low power asynchronous design methodology called MTNCL, which combines multi-threshold CMOS (MTCMOS) with NULL Convention Logic (NCL) systems. MTNCL provides the leakage power advantages of an all high-Vt implementation with a reasonable speed penalty compared to the all low-Vt implementation, and has negligible area overhead. The proposed tool utilizes industry-standard CAD tools. This research also presents an Automated Gate-Level Pipelining with Bit-Wise Completion (AGLPBW) method to maximize throughput of delay-insensitive full-word pipelined NCL circuits. These methods have been integrated into the Mentor Graphics and Synopsis CAD tools, using a C-program, which performs the majority of the computations, such that the method can be easily ported to other CAD tool suites. Both methods have been successfully tested on circuits, including a 4-bit × 4-bit multiplier, an unsigned Booth2 multiplier, and a 4-bit/8-operation arithmetic logic unit (ALU)
"]},{"key":"dc:title","label":"Title","values":["CAD Tool Design for NCL and MTNCL Asynchronous Circuits"]}]}],"canonical_facts":{"dc:contributor":["Brown, Randy L.","Mantooth, H. Alan"],"dc:contributor.advisor":["Smith, Scott C."],"dc:creator":["Pillai, Vijay Mani"],"dc:date":["2013"],"dc:date.available":["2017-09-29T07:00:00Z"],"dc:description.abstract":["This thesis presents an implementation of a method developed to readily convert Boolean designs into an ultra-low power asynchronous design methodology called MTNCL, which combines multi-threshold CMOS (MTCMOS) with NULL Convention Logic (NCL) systems. MTNCL provides the leakage power advantages of an all high-Vt implementation with a reasonable speed penalty compared to the all low-Vt implementation, and has negligible area overhead. The proposed tool utilizes industry-standard CAD tools. This research also presents an Automated Gate-Level Pipelining with Bit-Wise Completion (AGLPBW) method to maximize throughput of delay-insensitive full-word pipelined NCL circuits. These methods have been integrated into the Mentor Graphics and Synopsis CAD tools, using a C-program, which performs the majority of the computations, such that the method can be easily ported to other CAD tool suites. Both methods have been successfully tested on circuits, including a 4-bit × 4-bit multiplier, an unsigned Booth2 multiplier, and a 4-bit/8-operation arithmetic logic unit (ALU)
"],"dc:identifier":["https://scholarworks.uark.edu/etd/829"],"dc:subject":["Applied sciences","Asynchronous circuits","Bit-wise ncl","Bolean to mtncl","Cad tool design","Mtncl","Ncl","Digital Circuits","VLSI and Circuits, Embedded and Hardware Systems"],"dc:title":["CAD Tool Design for NCL and MTNCL Asynchronous Circuits"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["Master of Science in Electrical Engineering (MSEE)"]},"updated_at":"2026-07-24T00:59:58Z"}