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Showing 1 to 10 of 10 for “"Asynchronous circuits"”.

  1. Attacking complexity in logic synthesis of asynchronous circuits

    Most of the microelectronic circuits fabricated today are synchronous, i.e. they are driven by one or several clock signals. Synchronous circuit design faces several fundamental challenges such as high-speed clock distribution, integration of multiple cores operating at different clock rates, …

    potsdam-diss Repository record for Attacking complexity in logic synthesis of asynchronous circuits (opens in a new tab)

  2. CAD Tool Design for NCL and MTNCL Asynchronous Circuits

    … convert Boolean designs into an ultra-low power asynchronous design methodology called MTNCL, which combines multi-threshold CMOS (MTCMOS) with NULL Convention Logic (NCL) systems. MTNCL provides the leakage power advantages of an all high-Vt implementation with a reasonable speed penalty …

    arkansas Repository record for CAD Tool Design for NCL and MTNCL Asynchronous Circuits (opens in a new tab)

  3. Asynchronous 3D (Async3D): Design Methodology and Analysis of 3D Asynchronous Circuits

    … of 3D integrated circuit (IC) technology on asynchronous logic paradigms, mainly NULL Convention Logic (NCL) and Multi-Threshold NCL (MTNCL). It presents the Async3D tool flow and library for NCL and MTNCL 3D ICs. It also analyzes NCL and MTNCL circuits in 3D IC. Several FIR filter designs …

    arkansas Repository record for Asynchronous 3D (Async3D): Design Methodology and Analysis of 3D Asynchronous Circuits (opens in a new tab)

  4. Radiation-Hardened Delay-Insensitive Asynchronous Circuits for Multi-Bit SEU Mitigation and Data-Retaining SEL Protection

    … mechanisms. Delay-insensitive asynchronous circuits inherently have promising potentials in mitigating the effects of radiation due to their delay insensitivity. This thesis proposes the use of two delay-insensitive asynchronous logic architectures to mitigate the effects of up …

    arkansas Repository record for Radiation-Hardened Delay-Insensitive Asynchronous Circuits for Multi-Bit SEU Mitigation and Data-Retaining SEL Protection (opens in a new tab)

  5. Technology Mapping, Design for Testability, and Circuit Optimizations for NULL Convention Logic Based Architectures

    <p>Delay-insensitive asynchronous circuits have been the target of a renewed research effort because of the advantages they offer over traditional synchronous circuits. Minimal timing analysis, inherent robustness against power-supply, temperature, and process variations, reduced energy …

    arkansas Repository record for Technology Mapping, Design for Testability, and Circuit Optimizations for NULL Convention Logic Based Architectures (opens in a new tab)

  6. Asynchronous Data Processing Platforms for Energy Efficiency, Performance, and Scalability

    … design goals. Without clock-related issues, asynchronous circuits enable further design tradeoffs and in operation adaptive adjustments for energy efficiency. This dissertation work presents the design methodology of the asynchronous circuit using NULL Convention Logic (NCL) and …

    arkansas Repository record for Asynchronous Data Processing Platforms for Energy Efficiency, Performance, and Scalability (opens in a new tab)

  7. Testing of delay-insensitive circuits using protocol extraction strategies

    Delay-insensitive (DI) circuits are asynchronous circuits whose functional correctness is independent of the delays in their components and the interconnecting wires. The environment and circuit module follows a specified usage protocol, sometimes called handshake signals. It has been believed that …

    concordia Repository record for Testing of delay-insensitive circuits using protocol extraction strategies (opens in a new tab)

  8. Synthesis heuristics for large asynchronous sequential circuits

    "Many well-known synthesis procedures for asynchronous sequential circuits produce minimal or near-minimal results, but are practical only for very small problems. These algorithms become unwieldy when applied to "large" circuits with, for example, three or more input variables and twenty or more …

    must-thes Repository record for Synthesis heuristics for large asynchronous sequential circuits (opens in a new tab)