Asynchronous Data Processing Platforms for Energy Efficiency, Performance, and Scalability

<p>The global technology revolution is changing the integrated circuit industry from the one driven by performance to the one driven by energy, scalability and more-balanced design goals. Without clock-related issues, asynchronous circuits enable further design tradeoffs and in operation adaptive adjustments for energy efficiency. This dissertation work presents the design methodology of the asynchronous circuit using NULL Convention Logic (NCL) and multi-threshold CMOS techniques for energy efficiency and throughput optimization in digital signal processing circuits. Parallel homogeneous and heterogeneous platforms implementing adaptive dynamic voltage scaling (DVS) based on the observation of system fullness and workload prediction are developed for balanced control of the performance and energy efficiency. Datapath control logic with NULL Cycle Reduction (NCR) and arbitration network are incorporated in the heterogeneous platform for large scale cascading. The platforms have been integrated with the data processing units using the IBM 130 nm 8RF process and fabricated using the MITLL 90 nm FDSOI process. Simulation and physical testing results show the energy efficiency advantage of asynchronous designs and the effective of the adaptive DVS mechanism in balancing the energy and performance in both platforms.</p>

Name thesis:degree_name

Doctor of Philosophy in Engineering (PhD)

Level thesis:degree_level

Dissertation

Year dc:date.available

2016

Author dc:creator

• Men, Liang

Advisor dc:contributor.advisor

• Di, Jia

Contributors dc:contributor

• Thompson, Dale R.
• Parkerson, James P.

• Applied sciences
• Asynchronous circuit
• Energy efficiency
• High throughput
• Scalability
• Signal processing
• Digital Circuits
• VLSI and Circuits, Embedded and Hardware Systems

Repository record dc:identifier

https://scholarworks.uark.edu/etd/1666

OAI identifier oai:identifier

oai:scholarworks.uark.edu:etd-3205