Design and analysis of efficient MPSoC simulation techniques

During the last decade embedded systems have pervaded nearly all aspects of our daily lives. The advancements in digital information technologies and especially in mobile communications have been a main driver for this development. The evolution of the embedded systems has been driven by the improvements in deep submicron technology. These technology improvements enabled the system designers to integrate more and more functionality onto a single chip and thus satisfy the often conflicting requirements, e.g. low power consumption and high throughput. The downside of this high complexity are the high non recurrent engineering (NRE) costs and the ample amount of verification necessary for developing modern embedded systems. Only with the help of modern software tools such as compiler, simulator and debugger it is possible to guarantee short development cycles despite the growing complexity of the embedded systems. Due to the increased demand of flexibility for modern SoCs and the available computing power, the complexity of embedded software has been constantly growing over the years. By now, the growth of embedded software complexity has already outpaced the growth of the hardware HW complexity. Traditionally, the development of the embedded software can only start once a first hardware prototype of the target architecture is ready, leading to a purely sequential design flow. However, the shrinking time-to-market that can be observed especially in the consumer market, together with the increasing complexity of embedded systems requires a hardware/software co-design methodology in order to cope with the system complexity and the stringent time requirements of the projects. Virtual platforms (VP) are executable software models of hardware systems, allowing to simulate the entire system before it is built in real hardware. Thus, they can be utilized to develop and test embedded software efficiently, long before the complete system is ready in hardware. Using the VP concept it is possible to practically perform hardware/software co-design. Moreover, since VPs are pure software models of the hardware, they have the advantage that their internal states can be more easily observed and debugged, compared to a real hardware implementation. Like for all other types of simulation, the simulation speed of VPs is crucial for an efficient use. In the context of this work, three different approaches have been developed and implemented in order to efficiently simulate complex virtual platforms. Based on the observation that the required simulation accuracy changes over time while debugging an application, a hybrid simulation technique has been developed. This hybrid simulation technique enables the user to switch between a fast but inaccurate and a slow but detailed simulation. Hence, the software developer has the possibility to decide which parts of the application should be simulated in detail and which parts of the application should be executed at a high simulation speed. In order to speed up also detailed simulations a checkpoint/restore technique based on process checkpointing has been developed taking into account the specific requirements and characteristics of VPs. In particular, the dependencies between the simulation and the operating system need to be considered during the checkpointing process. This technique does not improve the simulation speed itself, but it can be utilized to reduce the time spent simulating by restoring previously saved states of the entire simulation environment. With the growing complexity of the MPSoCs also the complexity of the interconnect networks is growing and hence their impact on the simulation speed. Therefore, a hybrid network-on-chip (NoC) simulation approach has been developed that offers the software developer a slow and accurate NoC simulation or a fast and less accurate simulation mode. During the fast simulation mode the complete NoC is bypassed and the timing of the data transfers is estimated by an analytical NoC model based on queuing theory. A scalable NoC simulation framework has been used in order to study the impact of hybrid NoC simulation on the timing accuracy and the simulation speed.

Grantor dc:publisher

Publikationsserver der RWTH Aachen University

Year dc:date

2011

Author dc:creator

• Kraemer, Stefan

Contributors dc:contributor

• Leupers, Rainer

• info:eu-repo/classification/ddc/620
• Computersimulation
• Netzwerksimulation
• Entwurfsautomation
• SystemC
• Mehrebenensimulation
• Ingenieurwissenschaften
• virtuelle Plattformen
• Codeinstrumentierung
• hybride Simulation
• instruction set simulation
• virtual platforms
• code instrumentation
• hybrid simulation
• checkpoint/restore

Statement dc:rights

• info:eu-repo/semantics/openAccess

Language dc:language

eng

Identifier

https://publications.rwth-aachen.de/search?p=id:%22RWTH-CONV-114938%22

OAI record oai:identifier

https://publications.rwth-aachen.de/oai2d?verb=GetRecord&metadataPrefix=oai_dc&identifier=oai%3Apublications.rwth-aachen.de%3A52738