Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
Results
Showing 1 to 20 of 48 for “"Processor Architecture"”.
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Flexible MIPS soft processor architecture
The flexible MIPS soft processor architecture borrows selected technologies from high-performance computing to deliver a modular, highly customizable CPU targeted towards FPGA implementations for embedded systems; the objective is to provide a more flexible architectural alternative to …
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A generalized segment display processor architecture
Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1979.
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Database implementation on an object-oriented processor architecture
The advent of an object-oriented processor, the REKURSIV, allowed the possibility of investigating the application of object-oriented techniques to all the levels of a software system’s architecture. This work is concerned with the implementation of a database system on the REKURSIV. A database …
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Design of a Multibus Data-Flow Processor Architecture
… best solution. There is a need for specialized processor architectures for specific application areas. This thesis discusses the design of such a specialized processor architecture targeted towards event driven sensor applications. This thesis presents an augmented multibus dataflow processor …
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Design of a Power-aware Dataflow Processor Architecture
… of multiple sensors and a general purpose processor that handles the multiple events by deploying an event-driven software model. The software overheads of the general purpose processors results in energy inefficiency. What is needed is a class of special purpose processing elements which …
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Parallel processor architecture for a digital beacon receiver
A digital beacon receiver has been developed to monitor the OLYMPUS satellite beacons. The receiver accepts a nominal 10 MHz IF input and processes the signal using digital signal processing techniques. Fast Fourier transforms are used to locate the carrier within 0.5 Hz. The outputs of the …
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An Application Framework for a Power-Aware Processor Architecture
The instruction-set based general purpose processors are not energy-efficient for event-driven applications. The E-textiles group at Virginia Tech proposed a novel data-flow processor architecture design to bridge the gap between event-driven applications and the target architecture. The …
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A VLSI array processor architecture for emulating resistive network filtering
… of an all-transistor analogue parallel processor that emulates the functionality of a resistive network. The problems related to VLSI -implementations of parallel processors are the main concern of this thesis. These problems are first discussed and then to overcome these problems, a new …
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Superthreading: Integrating Compilation Technology and Processor Architecture for Cost-Effective Concurrent Multithreading
… the compiler techniques for superthreaded processors. Many existing compiler techniques used in traditional parallelizing compilers for multiprocessors as well as some specific compiler techniques for superthreaded processors are needed for generating superthreaded codes and enhancing …
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Design of an Automation Framework for a Novel Data-Flow Processor Architecture
… There is a need for specially designed architectures in application areas where the general purpose micro-controllers suffer from inefficiencies. This thesis focuses in the design of a processor architecture that provides a suitable design abstraction for a class of periodic, …
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An energy efficient sub-threshold baseband processor architecture for pulsed ultra-wideband communications
… to describe how operating the digital baseband processor in the sub-threshold region and increasing the degree of parallelism can translate into energy savings across the entire UWB receiver. While sub-threshold operation is traditionally used for low energy, low performance applications such as …
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A software system implementation guide and system prototyping facility for the MCORTEX executive on the real time cluster.
… time, concurrent software systems on a parallel processor architecture. The hierarchical bus parallel processor architecture, call the Real Time Cluster Star (RTC*), is the hardware on which an executive operating system, the Extended Multi-COmputer Real Time EXecutive (EMCORTEX), provides the …
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Architectural Support for Protecting Memory Integrity and Confidentiality
… efficient design of tamper-resistant secure processor and cryptographic memory protection model that will strength security of a computing system. The thesis proposes certain cryptographic and security features integrated into the general purpose processor and computing platform to protect …
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Simulation of a novel multiprocessor system based on dataflow principles
This thesis research is a study of a novel processor architecture for a massively parallel computer system. An existing simulation of the Fresh Breeze architecture has been extended to incorporate a multi-level memory hierarchy and dynamic load balancing. An efficient hardware-based garbage …
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Compact integrity-aware architectures
… using integrity kernels. Existing hardware architectures provide inadequate support for integrity kernels. Despite this, we equip commodity embedded systems with compact integrity kernels. We also describe the limitations of existing non-embedded processors. Then, we develop an extended …
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Multithreaded Natural Language Processing Tasks
… can be improved further in a multi-core processor architecture, where each thread runs in parallel on a different core. To benefit from the newer multi-core processors we can move towards multithreaded versions of traditional natural language processing systems. This thesis work has two …
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Formal Specification and Runtime Verification of Parallel Systems using Interval Temporal Logic (ITL)
… (PRVF) that can handle systems which use architectures of parallelism in their design such as multi-core processor architecture. The proposed model can check system behaviour at runtime in order to either guarantee satisfaction or detect violations of correctness properties. My technique …
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A VLSI systolic array processor for complex singular value decomposition
… maximum possible performance, a systolic array processor for computing the singular value decomposition of an arbitrary complex matrix was designed using a silicon compiler system. This system allows for ease of design by specification of the processor architecture in a high level language, …
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