Simulation of a novel multiprocessor system based on dataflow principles

This thesis research is a study of a novel processor architecture for a massively parallel computer system. An existing simulation of the Fresh Breeze architecture has been extended to incorporate a multi-level memory hierarchy and dynamic load balancing. An efficient hardware-based garbage collection mechanism has been proposed. Various design trade-offs are evaluated. The simulation demonstrates that the architecture can support memory access with DRAM latency and still achieve high processor utilization.

Department dc:contributor.department

Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2016

Author dc:creator

• Zhou, Mo, S.M. Massachusetts Institute of Technology

Advisor dc:contributor.advisor

• Jack B. Dennis.

• Electrical Engineering and Computer Science.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/106071

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/106071