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Virginia Tech

Parallel processor architecture for a digital beacon receiver

Abstract

dc:description.abstract

A digital beacon receiver has been developed to monitor the OLYMPUS satellite beacons. The receiver accepts a nominal 10 MHz IF input and processes the signal using digital signal processing techniques. Fast Fourier transforms are used to locate the carrier within 0.5 Hz. The outputs of the receiver include the frequency and the power of the carrier.

Degree

thesis:*
Name thesis:degree_name
Master of Science
Level thesis:degree_level
masters
Discipline thesis:degree_discipline
Electrical Engineering
Department dc:contributor.department
Electrical Engineering
Grantor dc:publisher
Virginia Tech
Year dc:date.issued
1990

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Runyon, Ginger R.

Rights

dc:rights
Statement dc:rights
  • In Copyright
Language dc:language.iso
en

Identifiers

dc:identifier.*
Dc Identifier Other
etd-03042009-040951
OAI identifier oai:identifier
oai:vtechworks.lib.vt.edu:10919/41422

Chain of custody

source
Harvested from
Virginia Tech
Base URL
vtechworks.lib.vt.edu/oai/request
Last updated
2026-07-22
Source record
OAI-PMH GetRecord
related terms
citation

Runyon, Ginger R.. Parallel processor architecture for a digital beacon receiver. masters thesis, Virginia Tech, 1990. http://hdl.handle.net/10919/41422