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Showing 1 to 20 of 34 for “"FPGA Design"”.
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Python based FPGA design-flow
… of using MyHDL as a basis on which to develop an FPGA-based DSP tool-ow to target CASPER hardware. MyHDL is an open-source package which enables Python to be used as a hardware definition and verification language. As Python is a high-level language, hardware designers can use it to model and …
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A Modular Flow for Rapid FPGA Design Implementation
This dissertation proposes an alternative FPGA design compilation flow to reduce the back-end time required to implement an FPGA design to below the level at which the user's attention is lost. To do so, this flow focuses on enforcing modular design for both productivity and code reuse, while …
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A Management Paradigm for FPGA Design Flow Acceleration
Advances in FPGA density and complexity have not been matched by a corresponding improvement in the performance of the implementation tools. Knowledge of incremental changes in a design can lead to fast turnaround times for implementing even large designs. A high-level overview of an incremental …
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JHDLBits: An Open-Source Model for FPGA Design Automation
Today's Field Programmable Gate Array (FPGA) research community could use an extensible tool flow enabling designers to examine new algorithms and new methods of interacting with FPGA configurations. One such flow is JHDLBits, which integrates two prominent FPGA design environments: JHDL and JBits. …
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FOpenCL: An optimized OpenCL-to-FPGA design flow for Xilinx SDx
… parallelism, have become more popular. GPU and FPGA are two significant examples of accelerators that provide high-degree parallelism and can yield significant speed-up if the developer properly understands the parallelism. However, in reality, it is very difficult to explore all the fine and …
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Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug
Design validation is the most time-consuming task in the FPGA design cycle. Although manufacturers and third-party vendors offer a range of tools that provide different perspectives of a design, many require that the design be fully re-implemented for even simple parameter modifications or do not …
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Module Shaping and Exploration in Rapid FPGA Design and Assembly Workflows
The modular design methodology has been widely adopted to harness the complexity of large FPGA-based systems. As a result, a number of commercial and academic tool flows emerged to support modular design including Hierarchical Design Flow and Partial Reconfiguration Flow, OpenPR, HMFlow, PARBIT, …
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Estimating the Dynamic Sensitive Cross Section of an FPGA Design through Fault injection
… behavior within the configuration memory of an FPGA. This tool is able to rapidly and accurately determine the dynamic sensitive cross section of the configuration memory for a given FPGA design. This tool enables the reliability of FPGA designs and fault tolerance schemes to be quickly and …
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Incremental Design Techniques with Non-Preemptive Refinement for Million-Gate FPGAs
… presents a Field Programmable Gate Array (FPGA) design methodology that can be used to shorten the FPGA design-and-debug cycle, especially as gate counts increase to many millions. Core-based incremental placement algorithms, in conjunction with fast interactive routing, are investigated to …
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An FPGA Software-Defined Ultra Wideband Transceiver
… the need for a test bed for UWB systems. An FPGA-based software-defined radio provides both post-fabrication definition of the radio and ample parallel processing power. This thesis presents the FPGA design for a software-defined radio targeted to impulse ultra-wideband signals. The system is …
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SEU-Induced Persistent Error Propagation in FPGAs
… characterize the dynamic SEU cross section of an FPGA design in terms of its persistent and non-persistent components. An SEU in the persistent cross section results in a permanent interruption of service until reset. An SEU in the non-persistent cross section causes a temporary interruption of …
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Modeling, simulation and implementation of a non-coherent binary-frequency-shift-keying (BFSK) receiver-transmitter into a field programmable gate array (FPGA)
… the use of a field programmable gate array (FPGA) to implement a non-coherent binary-frequency-shift-keyed receiver-transmitter (BFSK-RT) that simulates the modulation of the SINCGARS radio, the RT-1523C. An FPGA successfully, and with very few resources, implemented the desired modulation …
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A Reconfigurable Implementation of Bayesian Phylogenetic Inference
… keep up with the growing demands of biologists. FPGA co-processor architectures have been shown to effectively speed up the performance of software applications by performing the most time-consuming parts of the algorithm on custom hardware. The goal of this thesis is to investigate a …
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High speed DSP implementation in run-time partially reconfigurable FPGAs
… of utilizing a run-time partially reconfigurable FPGA to implement a sequence of high-speed digital signal processing filters. Rather than reconfiguring the entire device to modify part of a configuration, a modular architecture is designed to allow smaller segments of the device to be …
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An FPGA-based Run-time Reconfigurable 2-D Discrete Wavelet Transform Core
FPGAs provide an ideal template for run-time reconfigurable (RTR) designs. Only recently have RTR enabling design tools that bypass the traditional synthesis and bitstream generation process for FPGAs become available. The JBits tool suite is an environment that provides support for RTR designs on …
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Stream Communication and Computation in the Eight-meter-wavelength Transient Array (ETA) Radio Telescope
… array-based radio telescope. The instrument is designed to further astronomy by detecting and characterizing dispersed pulses received between 29–47 MHz. To aid data processing of radio signals received through 24 antennas, the ETA system performs real-time stream processing as data is passed …
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Automatic Instantiation and Timing-Aware Placement of Bus Macros for Partially Reconfigurable FPGA Designs
FPGA design implementation and debug tools have not kept pace with the advances in FPGA device density. The emphasis on area optimization and circuit speed has resulted in longer runtimes of the implementation tools. We address the implementation problem using a divide-and-conquer approach in which …
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Open-Source Bitstream Generation for FPGAs
… has traditionally been the single part of the FPGA design flow that has not been openly reproduced. This work enables bitstream generation for "limited" resources without reverse-engineering or violating End-User License Agreement terms. Two use cases in particular have motivated this …
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Implementation of DPA-Resistant Circuit for FPGA
In current Field-Programmable-Logic Architecture (FPGA) design flows, it is very hard to control the routing of submodules. It is thus very hard to make an identical copy of an existing circuit within the same FPGA fabric. We have solved this problem in a way that still enables us to modify the …
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A Toolkit for Rapid FPGA System Deployment
FPGA implementation tools have not kept pace with growing FPGA density. It is common for non-trivial designs to take multiple hours to go through the entire FPGA toolflow (synthesis, mapping, placement, routing, bitstream generation). FPGA implementation tool runtime is a major hindrance to FPGA …
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