Abstract
dc:description.abstractAdvances in FPGA density and complexity have not been matched by a corresponding improvement in the performance of the implementation tools. Knowledge of incremental changes in a design can lead to fast turnaround times for implementing even large designs. A high-level overview of an incremental productivity flow, focusing on the back-end FPGA design is provided in this thesis. This thesis presents a management paradigm that is used to capture the design specific information in a format that is reusable across the entire design process. A C++ based internal data structure stores all the information, whereas XML is used to provide an external view of the design data. This work provides a vendor independent, universal format for representing the logical and physical information associated with FPGA designs.
Degree
thesis:*- Name thesis:degree_name
- Master of Science
- Level thesis:degree_level
- masters
- Discipline thesis:degree_discipline
- Electrical and Computer Engineering
- Department dc:contributor.department
- Electrical and Computer Engineering
- Grantor dc:publisher
- Virginia Tech
- Year dc:date.issued
- 2011
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Tavaragiri, Abhay
- Chair dc:contributor.committeechair
-
- Athanas, Peter M.
- Committee members dc:contributor.committeemember
-
- Schaumont, Patrick R.
- Tront, Joseph G.
Subjects
dc:subject × 4Rights
dc:rights- Statement dc:rights
-
- In Copyright
- Licence dc:rights.uri
Identifiers
dc:identifier.*- Dc Identifier Other
- etd-07072011-145912
- OAI identifier oai:identifier
- oai:vtechworks.lib.vt.edu:10919/33923