Design methodology for electron-trap memory cells

It is widely known that the decreasing feature size facilitated vast improvement in semiconductor-based design. But this improvement will eventually come to an end. The MOS transistor itself cannot overcome its limits dictated by its operating principle. In order to ensure further feature size reduction, the field of single-electronics has been developed. Single Electron Tunneling (SET) technology offers the ability to control the transport and position of a single or a small number of electrons. In this thesis we investigate the implementation of arithmetic operations in SET technology. In particular we focus on design methodologies for SET based Electron-Trap which is a basic memory cell that has been recently fabricated. Given a circuit topology and the corresponding targeted behaviour, the proposed methodology assists the circuit designer in deriving the circuit parameters in an analytical way. The methodology is based on the mathematical description of the tunnel junctions in the circuit. Moreover the method allows for the analysis of reliability issues.

Name thesis:degree_name

M.A.Sc.

Level thesis:degree_level

Masters

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Grantor

University of Windsor

Year dc:date.issued

2008

Author dc:creator

• Bingxi, Li

Advisor dc:contributor.advisor

• Chen, Chunhong

Licence

• http://creativecommons.org/licenses/by-nc-nd/4.0/

Language dc:language.iso

en_CA

Handle dc:identifier.uri

https://hdl.handle.net/20.500.14776/1228

OAI identifier oai:identifier

oai:uwindsor.scholaris.ca:20.500.14776/1228