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Virginia Polytechnic Institute and State University

Optimal constructs for chip level modeling

Abstract

dc:description.abstract

Analysis and comparison of nine different Hardware Description Languages is presented. Comparison features are discussed and each language is analysed according to the comparison features, which are: sequencing mechanisms, applicability to generic structures, abstraction of data and operation, timing mode, communication mechanisms, and instantiation and interconnection of elements. Based on the analysis of the languages, optimal constructs for chip level modeling are extracted. Example descriptions of a microprocessor system MARK 2 are presented.

Degree

thesis:*
Name thesis:degree_name
M.S.
Level thesis:degree_level
masters
Discipline thesis:degree_discipline
Electrical Engineering
Department dc:contributor.department
Electrical Engineering
Grantor dc:publisher
Virginia Polytechnic Institute and State University
Year dc:date.issued
1986

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Han, Dongil

Rights

dc:rights
Statement dc:rights
  • In Copyright
Language dc:language.iso
en_US

Identifiers

dc:identifier.*
Handle dc:identifier.uri
http://hdl.handle.net/10919/94469
OAI identifier oai:identifier
oai:vtechworks.lib.vt.edu:10919/94469

Chain of custody

source
Harvested from
Virginia Tech
Base URL
vtechworks.lib.vt.edu/oai/request
Last updated
2026-07-22
Source record
OAI-PMH GetRecord
related terms
citation

Han, Dongil. Optimal constructs for chip level modeling. masters thesis, Virginia Polytechnic Institute and State University, 1986. http://hdl.handle.net/10919/94469