Micro-operation perturbations in chip level fault modeling

In chip level testing using hardware description language approach, a difficult question to answer is: What is the best micro-operation perturbation for modeling fault at the chip level? In this thesis, an automatic evaluation system is developed to determine the best micro-operation perturbation. The measure used is the gate level stuck-at fault coverage achieved by the tests derived to cover the micro-operation perturbation faults. For small combinational circuits, it is shown that perturbing the elements into the logic dual is a good choice. For large combinational circuits, it is shown that there is very little variation in the gate level coverage achieved by the various microoperation faults. In this case, if coverage is to be improved, the micro-operation perturbation method must be augmented by other techniques.

Name thesis:degree_name

Master of Science

Level thesis:degree_level

masters

Discipline thesis:degree_discipline

Electrical Engineering

Department dc:contributor.department

Electrical Engineering

Grantor dc:publisher

Virginia Polytechnic Institute and State University

Year dc:date.issued

1988

Author dc:creator

• Chao, Chien-Hung

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Language dc:language.iso

en_US

Handle dc:identifier.uri

http://hdl.handle.net/10919/80061

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/80061