Fault tolerant clocking system

The distributions of synchronized clock signals to all elements of a computing system is very important. Fletcher's clock patent is a good solution to this problem. The difficulty with implementation is the tremendous number of interconnections among different clock elements. Two methods are proposed to reduce the number of interconnectons without loss of synchronization and fault-tolerant capability. An mth order clock is a circuit consisting of (3f+1) ** (2** (m-1)) (m-1)th order clocks. Fletcher's clock patent is a 0th order clock. Starting with 0th order clocks, an mth order clock circuit can be built systematically. An mth order clock circuit can generate (3f+1)**(2**m) synchronized clock signals with (m + 1) (3f+ 1) ** ( 2**m) interconnections instead of (3f+1) ** (2*2**m) • Its fault-tolerant capability is also considered. Another type of connection is called Iterative Type, which is further classified into Cascaded Type, Scattering Type and 2-dimensional Type. Each type has its own characteristics.

Name thesis:degree_name

Master of Science

Level thesis:degree_level

masters

Discipline thesis:degree_discipline

Electrical Engineering

Department dc:contributor.department

Electrical Engineering

Grantor dc:publisher

Virginia Polytechnic Institute and State University

Year dc:date.issued

1978

Author dc:creator

• Fan, Tzu-I Jonathan

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Language dc:language.iso

en

Handle dc:identifier.uri

http://hdl.handle.net/10919/76003

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/76003